myhdl-list

[myhdl-list] Converting std_logic_vector to signed and vice versa

[Thomas H. <th...@ct...>]

I have written a small module in MyHDL which takes
incoming waveforms x and y, multiplies them with an
amplitude value and adds an offset tho them.

The VHDL code that MyHDL generates uses signed(15 downto 0)
for the values:

entity DSP is
     port (
         clock: in std_logic;
         x: in signed (15 downto 0);
         y: in signed (15 downto 0);
         amplitude: in signed (15 downto 0);
         offset: in signed (15 downto 0);
         xout: out signed (15 downto 0);
         yout: out signed (15 downto 0)
     );
end entity DSP;

Now, my top level module uses std_logic_vector(15 downto 0)
for these signals.  How can I use the generated module?

Thanks,
Thomas

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Alain P. <ala...@sp...>]

Hi Thomas,

to_integer() converts unsigned or signed values to natural or integer values, respectively.
Then convert with

function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
  tmp := std_logic_vector(to_unsigned(i, w));
  return(tmp);
end;

for instance to a the std_logic_vector (refer to gaisler lib grlib).

Hope that helps.

Cheers
Alain

> -----Original Message-----
> From: Thomas Heller [mailto:th...@ct...]
> Sent: Friday, January 07, 2011 7:52 PM
> To: myh...@li...
> Subject: [myhdl-list] Converting std_logic_vector to signed and vice
> versa
> 
> I have written a small module in MyHDL which takes
> incoming waveforms x and y, multiplies them with an
> amplitude value and adds an offset tho them.
> 
> The VHDL code that MyHDL generates uses signed(15 downto 0)
> for the values:
> 
> entity DSP is
>      port (
>          clock: in std_logic;
>          x: in signed (15 downto 0);
>          y: in signed (15 downto 0);
>          amplitude: in signed (15 downto 0);
>          offset: in signed (15 downto 0);
>          xout: out signed (15 downto 0);
>          yout: out signed (15 downto 0)
>      );
> end entity DSP;
> 
> Now, my top level module uses std_logic_vector(15 downto 0)
> for these signals.  How can I use the generated module?
> 
> Thanks,
> Thomas
> 
> 
> -----------------------------------------------------------------------
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Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Kevin S. <sta...@gm...>]

The signed type is a subtype of std_logic_vector (see the ieee.numeric_std
package). Assuming you can used a signed binary word throughout, there
should be no need to convert to std_logic_vector, unless you need to do
arithmetic elsewhere that is unsigned and you wish to convert it to unsigned
format.

Kevin

On Fri, Jan 7, 2011 at 12:52 PM, Thomas Heller <th...@ct...> wrote:

> I have written a small module in MyHDL which takes
> incoming waveforms x and y, multiplies them with an
> amplitude value and adds an offset tho them.
>
> The VHDL code that MyHDL generates uses signed(15 downto 0)
> for the values:
>
> entity DSP is
>     port (
>         clock: in std_logic;
>         x: in signed (15 downto 0);
>         y: in signed (15 downto 0);
>         amplitude: in signed (15 downto 0);
>         offset: in signed (15 downto 0);
>         xout: out signed (15 downto 0);
>         yout: out signed (15 downto 0)
>     );
> end entity DSP;
>
> Now, my top level module uses std_logic_vector(15 downto 0)
> for these signals.  How can I use the generated module?
>
> Thanks,
> Thomas
>
>
>
> ------------------------------------------------------------------------------
> Gaining the trust of online customers is vital for the success of any
> company
> that requires sensitive data to be transmitted over the Web.   Learn how to
> best implement a security strategy that keeps consumers' information secure
> and instills the confidence they need to proceed with transactions.
> http://p.sf.net/sfu/oracle-sfdevnl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Kevin R. Stanton
c | 734•846•3915
e | sta...@gm...

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Thomas H. <th...@ct...>]

 >> entity DSP is
 >>      port (
 >>          clock: in std_logic;
 >>          x: in signed (15 downto 0);
 >>          y: in signed (15 downto 0);
 >>          amplitude: in signed (15 downto 0);
 >>          offset: in signed (15 downto 0);
 >>          xout: out signed (15 downto 0);
 >>          yout: out signed (15 downto 0)
 >>      );
 >> end entity DSP;


Am 07.01.2011 20:28, schrieb Kevin Stanton:
> The signed type is a subtype of std_logic_vector (see the ieee.numeric_std
> package). Assuming you can used a signed binary word throughout, there
> should be no need to convert to std_logic_vector, unless you need to do
> arithmetic elsewhere that is unsigned and you wish to convert it to unsigned
> format.

Kevin,

what does this mean?  If I create a VHDL instantiation template for the
DSP then xilinx ISE creates this component declaration:

	COMPONENT DSP
	PORT(
		clock : IN std_logic;
		x : IN std_logic_vector(15 downto 0);
		y : IN std_logic_vector(15 downto 0);
		amplitude : IN std_logic_vector(15 downto 0);
		offset : IN std_logic_vector(15 downto 0);
		xout : OUT std_logic_vector(15 downto 0);
		yout : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

I thought it is a bug that ISE generates std_logic_vector types instead
of signed; do you mean that this is ok?

Thomas

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Kevin S. <sta...@gm...>]

I don't have time to test this right now and I can't recall for sure, but
this is from http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#vec_conversion

Note that the types std_logic_vector, std_ulogic_vector, signed and unsigned
are all closely related to each other (see FAQ Part 4 -
B.40<http://www.vhdl.org/comp.lang.vhdl/FAQ4.html#closely related
types>
 and Section 4.2.18<http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#ambiguous_expressions>).
Hence, the explicit conversion can be used to transform the types as
needed--no conversion functions are, in fact required (although they are
provided by the packages std_logic_1164 and numeric_std). An example showing
the use of explicit conversion is:


        variable slv_vec  : std_logic_vector(0 to 7);
        variable sulv_vec : std_ulogic_vector(0 to 7);
        variable uns_vec  : unsigned(0 to 7);
        variable sgn_vec  : signed(0 to 7);
        ...
        slv_vec  := std_logic_vector(sulv_vec);
        sulv_vec := std_ulogic_vector(slv_vec);
        slv_vec  := std_logic_vector(uns_vec);
        slv_vec  := std_logic_vector(sgn_vec);
        uns_vec  := unsigned(slv_vec);
        sgn_vec  := signed(sulv_vec);
        uns_vec  := unsigned(sgn_vec);




I don't believe any conversion needs to take place, you can simply cast it
as a std_logic_vector.

Let me know if you need more help,

Kevin

On Fri, Jan 7, 2011 at 2:11 PM, Thomas Heller <th...@ct...> wrote:

>  >> entity DSP is
>  >>      port (
>  >>          clock: in std_logic;
>  >>          x: in signed (15 downto 0);
>  >>          y: in signed (15 downto 0);
>  >>          amplitude: in signed (15 downto 0);
>  >>          offset: in signed (15 downto 0);
>  >>          xout: out signed (15 downto 0);
>  >>          yout: out signed (15 downto 0)
>  >>      );
>  >> end entity DSP;
>
>
> Am 07.01.2011 20:28, schrieb Kevin Stanton:
> > The signed type is a subtype of std_logic_vector (see the
> ieee.numeric_std
> > package). Assuming you can used a signed binary word throughout, there
> > should be no need to convert to std_logic_vector, unless you need to do
> > arithmetic elsewhere that is unsigned and you wish to convert it to
> unsigned
> > format.
>
> Kevin,
>
> what does this mean?  If I create a VHDL instantiation template for the
> DSP then xilinx ISE creates this component declaration:
>
>        COMPONENT DSP
>        PORT(
>                clock : IN std_logic;
>                x : IN std_logic_vector(15 downto 0);
>                y : IN std_logic_vector(15 downto 0);
>                amplitude : IN std_logic_vector(15 downto 0);
>                offset : IN std_logic_vector(15 downto 0);
>                xout : OUT std_logic_vector(15 downto 0);
>                yout : OUT std_logic_vector(15 downto 0)
>                );
>        END COMPONENT;
>
> I thought it is a bug that ISE generates std_logic_vector types instead
> of signed; do you mean that this is ok?
>
> Thomas
>
>
>
> ------------------------------------------------------------------------------
> Gaining the trust of online customers is vital for the success of any
> company
> that requires sensitive data to be transmitted over the Web.   Learn how to
> best implement a security strategy that keeps consumers' information secure
> and instills the confidence they need to proceed with transactions.
> http://p.sf.net/sfu/oracle-sfdevnl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Kevin R. Stanton
c | 734•846•3915
e | sta...@gm...

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> I have written a small module in MyHDL which takes
> incoming waveforms x and y, multiplies them with an
> amplitude value and adds an offset tho them.
> 
> The VHDL code that MyHDL generates uses signed(15 downto 0)
> for the values:
> 
> entity DSP is
>      port (
>          clock: in std_logic;
>          x: in signed (15 downto 0);
>          y: in signed (15 downto 0);
>          amplitude: in signed (15 downto 0);
>          offset: in signed (15 downto 0);
>          xout: out signed (15 downto 0);
>          yout: out signed (15 downto 0)
>      );
> end entity DSP;
> 
> Now, my top level module uses std_logic_vector(15 downto 0)
> for these signals.  How can I use the generated module?

signed, unsigned, and std_logic_vector are in VHDL terminology
"closely related". This implies that you can directly convert
them to each other using the target type name as a casting function.

For minimal overhead, the type conversions can be done right
in the instantiation. They work at both sides of a named
association, i.e. for both formal and actual.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> I have written a small module in MyHDL which takes
> incoming waveforms x and y, multiplies them with an
> amplitude value and adds an offset tho them.
> 
> The VHDL code that MyHDL generates uses signed(15 downto 0)
> for the values:
> 
> entity DSP is
>      port (
>          clock: in std_logic;
>          x: in signed (15 downto 0);
>          y: in signed (15 downto 0);
>          amplitude: in signed (15 downto 0);
>          offset: in signed (15 downto 0);
>          xout: out signed (15 downto 0);
>          yout: out signed (15 downto 0)
>      );
> end entity DSP;
> 
> Now, my top level module uses std_logic_vector(15 downto 0)
> for these signals.  How can I use the generated module?

signed, unsigned, and std_logic_vector are in VHDL terminology
"closely related". This implies that you can directly convert
them to each other using the target type name as a casting function.

For minimal overhead, the type conversions can be done right
in the instantiation. They work at both sides of a named
association, i.e. for both formal and actual.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Jan D. <ja...@ja...>]

Kevin Stanton wrote:
> The signed type is a subtype of std_logic_vector (see the 
> ieee.numeric_std package). Assuming you can used a signed binary word 
> throughout, there should be no need to convert to std_logic_vector, 
> unless you need to do arithmetic elsewhere that is unsigned and you wish 
> to convert it to unsigned format.

signed is not a subtype of std_logic_vector. However, type
conversions between the two are trivial because they are
closely related, meaning that you can cast using the
target type name as a conversion function.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Kevin S. <sta...@gm...>]

>signed is not a subtype of std_logic_vector. However, type
>conversions between the two are trivial because they are
>closely related, meaning that you can cast using the
>target type name as a conversion function.

Ah yes, but both are types made up of arrays of std_logic.

On Mon, Jan 10, 2011 at 2:19 AM, Jan Decaluwe <ja...@ja...> wrote:

> Kevin Stanton wrote:
> > The signed type is a subtype of std_logic_vector (see the
> > ieee.numeric_std package). Assuming you can used a signed binary word
> > throughout, there should be no need to convert to std_logic_vector,
> > unless you need to do arithmetic elsewhere that is unsigned and you wish
> > to convert it to unsigned format.
>
> signed is not a subtype of std_logic_vector. However, type
> conversions between the two are trivial because they are
> closely related, meaning that you can cast using the
> target type name as a conversion function.
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> Gaining the trust of online customers is vital for the success of any
> company
> that requires sensitive data to be transmitted over the Web.   Learn how to
> best implement a security strategy that keeps consumers' information secure
> and instills the confidence they need to proceed with transactions.
> http://p.sf.net/sfu/oracle-sfdevnl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Kevin R. Stanton
c | 734•846•3915
e | sta...@gm...