myhdl-list

[myhdl-list] understanding Signal and intbv

[Thomas H. <th...@ct...>]

I have a 4-bit wide bus:

   bus = Signal(intbv(0)[4:])

I cannot find out how to split the bus into single bits (or parts)
so that I can connect them to instances.  For example:

   def xor(a, b, q):
       @always_comb
       def inst():
           q.next = a ^ b
       return inst

   output = Signal(False)

   gate = xor(bus[1:0], bus[2:0], output)

bus[0] returns the current value of bit 0 and not the bus signal itself, 
bus[1:0] returns a completely _new_ intbv object.

How would I do this?

Thanks,
Thomas

Re: [myhdl-list] understanding Signal and intbv

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> I have a 4-bit wide bus:
> 
>    bus = Signal(intbv(0)[4:])
> 
> I cannot find out how to split the bus into single bits (or parts)
> so that I can connect them to instances.  For example:
> 
>    def xor(a, b, q):
>        @always_comb
>        def inst():
>            q.next = a ^ b
>        return inst
> 
>    output = Signal(False)
> 
>    gate = xor(bus[1:0], bus[2:0], output)
> 
> bus[0] returns the current value of bit 0 and not the bus signal itself, 
> bus[1:0] returns a completely _new_ intbv object.
> 
> How would I do this?

Short answer: in 0.7, you can use the Signal call interface
to construct implicit signals that work as expected in structure.

Longer answer:

This is what I consider to be MyHDL's most important gotcha.
In MyHDL 0.7, I introduce a solution called ShadowSignals - however
be warned that it's not as intuitive as with compiled HDLs, where
the meaning of slicing can be derived from the code context
by a compiler.

Background info starting point:

    http://www.myhdl.org/doc/dev/whatsnew/0.7.html#shadow-signals


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] understanding Signal and intbv

[Thomas H. <th...@ct...>]

Am 12.11.2010 11:18, schrieb Jan Decaluwe:
> Thomas Heller wrote:
>> I cannot find out how to split the bus into single bits (or parts)
>> so that I can connect them to instances.
[...]
>
> Short answer: in 0.7, you can use the Signal call interface
> to construct implicit signals that work as expected in structure.
>
> Longer answer:
>
> This is what I consider to be MyHDL's most important gotcha.
> In MyHDL 0.7, I introduce a solution called ShadowSignals - however
> be warned that it's not as intuitive as with compiled HDLs, where
> the meaning of slicing can be derived from the code context
> by a compiler.
>
> Background info starting point:
>
>      http://www.myhdl.org/doc/dev/whatsnew/0.7.html#shadow-signals
>
Thanks, Jan, for this answer.  0.7 seems to work as expected.
I have to believe you that it is a good decision to make ShadowSignals
readonly, but let me ask one question:

Why can't you use slicing/indexing notation to create a shadow signal?
Performance?  Backwards compatibility?  Education of the programmer?
Or is it simply not possible?

It seems a little error-prone having to use the call interface in one
case and the indexing notation in the other case.

Thanks,
Thomas

Re: [myhdl-list] understanding Signal and intbv

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> Am 12.11.2010 11:18, schrieb Jan Decaluwe:
>> Thomas Heller wrote:
>>> I cannot find out how to split the bus into single bits (or parts)
>>> so that I can connect them to instances.
> [...]
>> Short answer: in 0.7, you can use the Signal call interface
>> to construct implicit signals that work as expected in structure.
>>
>> Longer answer:
>>
>> This is what I consider to be MyHDL's most important gotcha.
>> In MyHDL 0.7, I introduce a solution called ShadowSignals - however
>> be warned that it's not as intuitive as with compiled HDLs, where
>> the meaning of slicing can be derived from the code context
>> by a compiler.
>>
>> Background info starting point:
>>
>>      http://www.myhdl.org/doc/dev/whatsnew/0.7.html#shadow-signals
>>
> Thanks, Jan, for this answer.  0.7 seems to work as expected.
> I have to believe you that it is a good decision to make ShadowSignals
> readonly, but let me ask one question:

It's not really a decision - it's more that I can't figure out how
"writing" should work. Note that shadow signals really "follow" their
parents with one delta cycle. That is easy to do. But the inverse?
All kinds of issues pop up. Reading and writing are not symmetric.

Fortunately, I think, "following" is what we normally need. And
ConcatSignal's can sort of emulate the inverse of slicing.

> Why can't you use slicing/indexing notation to create a shadow signal?
> Performance?  Backwards compatibility?  Education of the programmer?
> Or is it simply not possible?

Suppose I would return a _SliceSignal shadow signal whenever a signal
is sliced. Now consider the case of slicing inside a generator. The only
thing you need (in traditional HDL design) is the current value of the slice.
But to obtain that, you would go through the whole process of creating
a Signal, which means all kinds of datastructures that will never be
used. And this everytime you slice, typically over and over again
during a simulation. I haven't run actual tests, but it seems obvious
this is simply unacceptable performance-wise.

You can create Signals on the fly during simulation if you want to
(unlike compiled HDLs), but creating them without using any of the
services that they are designed for is really not the intention.

> It seems a little error-prone having to use the call interface in one
> case and the indexing notation in the other case.

I agree again that it's awkward to have the two notations.

On the other hand:
With my VHDL-influenced HDL hat on, signals are really "static" things
created once before the simulation starts and that then live on "forever".
Outside generators, I think structure and signals. Inside them
I think variables and values. ShadowSignals are part of the structure,
regular slicing of generator behavior. The call interface suggest
that something new is "constructed" which is what really happens
with this workaround.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com