Christopher L. Felton schrieb:
> On 7/25/2010 5:43 AM, Thomas Heller wrote:
>> I'm trying to model a phase frequency detector like the one
>> in Figure 1 of this article:
>>
>> http://www.analog.com/library/analogDialogue/archives/33-07/phase3/
>>
>> IMO the VHDL code would be something like this:
>>
>> process(in_a, in_b, up, down)
>> begin
>> if up = '1' and down = '1' then
>> up<= '0';
>> down<= '0';
>> else
>> if rising_edge(in_a) then
>> up<= '1';
>> end if;
>> if rising_edge(in_b) then
>> down<= '1';
>> end if;
>> end if;
>> end process;
>>
>> How would I code this in myhdl?
>>
>>
> In your VHDL process you specify 3 signals in the sensitivity list.
> Two of the signals are qualified to be rising edge sensitive. In MyHDL
> you can do the similar thing.
>
> @always(in_a.posedge, in_b.posedge, up, down)
> def rtl_pfd():
> if up and down:
> up.next = False
> down.next = False
> if in_a:
> up.next = True
> if in_b:
> down.next = True
>
>
> I didn't test the above, I need to double check the the level sensitive
> syntax is @always(sig, sig, ...).
I don't think this will work. Here is a quote from the MyHDL manual:
"""
... this is MyHDL code for a D flip-flop with asynchronous set,
asynchronous reset, and preference of set over reset:
@always(clk.posedge, set.negedge, rst.negedge)
def logic():
if set == 0:
q.next = 1
elif rst == 0:
q.next = 0
else:
q.next = d
"""
As you can see, there is NO edge-test inside the 'logic' function. If I understand
the working of the above DFF correctly, it goes like this:
The 'logic()' function is called when clk goes HIGH, or when SET or RESET goes low.
The values of the SET and RESET signals are examined, if the are LOW then the corresponding
action is taken. If both are HIGH then the last else clause is executed which must now
be the positive edge of the clk signal.
So, maybe the question boils down to this:
If I have more than one edge sensitive signal in the always decorator, how do I test
in the function block which of these edges have occurred?
--
Thanks,
Thomas
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