myhdl-list

[myhdl-list] cosimulation trouble

[Neal B. <ndb...@gm...>]

Now I'm moving on to trying cosim.  I have installed icarus, compiled 
myhdl.vpi.  When run with normal sim result is fine, but when run as cosim I 
get no error, but nothing happens (I have a counter and an accumulator - the 
count never increments and the accumulator output never changes).  Any 
ideas?  Any hints at how to troubleshoot this?

Here is the code:
from myhdl import Signal, always, intbv, Simulation, delay, toVerilog, 
traceSignals, always_comb, instance



def Counter (count, clock, n):
    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

#        print "count:", count
    return cntLogic

def accum (x, result, count, clock, n):
    _sum = Signal (intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        _sum.next = _sum + x
        if count == n-1:
            ##print 'count:', count, 'sum:', _sum
            result.next = _sum
            _sum.next = 0

    return accum_logic

def Decimator (clock, x, n, count, result):
    cnt1 = Counter (count, clock, n)
    acc1 = accum (x, result, count, clock, n)
    return cnt1, acc1

def testbench(dut, clock, count, x, result):
    HALF_PERIOD = delay(1)

    
#    decimator1 = Decimator (clock, x, n, count, result)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            x.next = 1
        
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'x:', x, 'count:', count, 'result:', result

    return clockGen, stimulus, monitor, dut


def main():
    n = 16
    x = Signal (intbv(0)[4:])
    #clock = Signal()
    clock = Signal (intbv(0)[1:])
    result = Signal(intbv(0)[8:])
    count = Signal (intbv(0)[4:])
    dut = Decimator (clock, x, n, count, result)
    tb = traceSignals (testbench, dut, clock, count, x, result)

    Simulation(tb).run(50)

def cosim():
    n = 16
    x = Signal (intbv(0)[4:])
    #clock = Signal()
    clock = Signal (intbv(0)[1:])
    result = Signal(intbv(0)[8:])
    count = Signal (intbv(0)[4:])
    from co import Decimator_v
    dut = Decimator_v (clock, x, n, count, result)

    tb = testbench (dut, clock, count, x, result)
    Simulation (tb).run (50)
#mode = 'sim'
#mode = 'test'
mode = 'cosim'

if __name__ == '__main__':
    if (mode == 'verilog'):
         n = 16 
         x      = Signal(intbv(0)[4:]) 
         clock  = Signal(False) 
         result = Signal(intbv(0)[8:]) 
         count  = Signal(intbv(0)[4:]) 

         #dut = Decimator (clock, x, n, count, result) 
         toVerilog(Decimator, clock, x, n, count, result) 
    elif mode == "test":
        toVerilog (testbench)
    elif mode == "sim":
        main()
    elif mode == "cosim":
        cosim()

And here is co.py:
from myhdl import *
from test3 import Decimator
import os

def Decimator_v(clock, x, n, count, result):
    toVerilog(Decimator, clock, x, n, count, result)
    cmd = "iverilog -o Decimator tb_Decimator.v Decimator.v"
    os.system (cmd)
    
    return Cosimulation("vvp -v -m ./myhdl.vpi Decimator", **locals())

Here's what I get when mode = 'sim':
python test3.py
x: 0 count: 0 result: 0
x: 1 count: 1 result: 0
x: 1 count: 2 result: 0
x: 1 count: 3 result: 0
x: 1 count: 4 result: 0
x: 1 count: 5 result: 0
x: 1 count: 6 result: 0
x: 1 count: 7 result: 0
x: 1 count: 8 result: 0
x: 1 count: 9 result: 0
x: 1 count: 10 result: 0
x: 1 count: 11 result: 0
x: 1 count: 12 result: 0
x: 1 count: 13 result: 0
x: 1 count: 14 result: 0
x: 1 count: 15 result: 0
x: 1 count: 0 result: 14
x: 1 count: 1 result: 14
x: 1 count: 2 result: 14
x: 1 count: 3 result: 14
x: 1 count: 4 result: 14
x: 1 count: 5 result: 14
x: 1 count: 6 result: 14
x: 1 count: 7 result: 14
x: 1 count: 8 result: 14
<class 'myhdl._SuspendSimulation'>: Simulated 50 timesteps

For mode = 'cosim':

 python test3.py
** ToVerilogWarning: Output port is read internally: count
Compiling VVP ...
 ... VVP file version 0.9.devel (s20080905-418-g1c17412)
Compile cleanup...
 ... Linking
 ... Removing symbol tables
 ... Compiletf functions
 ...       10 functors (net_fun pool=0 bytes)
                  0 logic
                  0 bufif
                  0 resolv
                  9 signals
 ...       42 opcodes (24576 bytes)
 ...        9 nets
 ...       10 vvp_nets (1048560 bytes)
 ...        0 arrays (0 words)
 ...        0 memories
                  0 logic (0 words)
                  0 real (0 words)
 ...        4 scopes
 ... 0.001 seconds, 36420.0/3340.0/1296.0 KBytes size/rss/shared
Running ...
x: 0 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
<class 'myhdl._SuspendSimulation'>: Simulated 50 timesteps
 ... 0.002 seconds, 36420.0/3496.0/1448.0 KBytes size/rss/shared
Event counts:
         203 time steps (pool=146)
         128 thread schedule events
          55 assign events
             ...assign(vec4) pool=9362
             ...assign(vec8) pool=204
             ...assign(real) pool=256
             ...assign(word) pool=128
         353 other events (pool=4096)

Re: [myhdl-list] cosimulation trouble

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Now I'm moving on to trying cosim.  I have installed icarus, compiled 
> myhdl.vpi.  When run with normal sim result is fine, but when run as cosim I 
> get no error, but nothing happens (I have a counter and an accumulator - the 
> count never increments and the accumulator output never changes).  Any 
> ideas?  Any hints at how to troubleshoot this?

Typically, the situation where "nothing happens" is caused by initialization
issues. In particular, in Verilog everything starts at 'X' by default, while
in MyHDL, the start value is defined.

In this case, I guess count starts at 'X', and as it is not explicitly
reset, it stays at 'X'. Also, no events are generated to the MyHDL side,
so count seems to keep its starting value.

The solution is to use an explicit reset signal that brings the circuit
into a known state.

At the RTL level and higher, the MyHDL convertor could in fact generate
initialization values with the Verilog declarations to bring the Verilog
code more in line with MyHDL at time 0. The only reason why this isn't
done it that at one point it was reported that some synthesis tools
don't support that (I think it was the tool from Altera). I'm interested
in hearing whether that's still the case.

At the gate level, you would always need the reset signal though.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] cosimulation trouble

[Neal B. <ndb...@gm...>]

Jan Decaluwe wrote:

> Neal Becker wrote:
>> Now I'm moving on to trying cosim.  I have installed icarus, compiled
>> myhdl.vpi.  When run with normal sim result is fine, but when run as
>> cosim I get no error, but nothing happens (I have a counter and an
>> accumulator - the
>> count never increments and the accumulator output never changes).  Any
>> ideas?  Any hints at how to troubleshoot this?
> 
> Typically, the situation where "nothing happens" is caused by
> initialization issues. In particular, in Verilog everything starts at 'X'
> by default, while in MyHDL, the start value is defined.
> 
> In this case, I guess count starts at 'X', and as it is not explicitly
> reset, it stays at 'X'. Also, no events are generated to the MyHDL side,
> so count seems to keep its starting value.
> 
> The solution is to use an explicit reset signal that brings the circuit
> into a known state.
> 
> At the RTL level and higher, the MyHDL convertor could in fact generate
> initialization values with the Verilog declarations to bring the Verilog
> code more in line with MyHDL at time 0. The only reason why this isn't
> done it that at one point it was reported that some synthesis tools
> don't support that (I think it was the tool from Altera). I'm interested
> in hearing whether that's still the case.
> 
> At the gate level, you would always need the reset signal though.
> 
> Jan
> 

I'm confused here.  count is both in and out from 'Counter'.  Counter is 
instantiated in 'Decimator', which is instantiated in the top-level of 
'cosim'.  There, count is initialized to 0.  What would I need to change?  
Why is it that in 'Counter' myhdl flags 'count' as output rather than inout?

Re: [myhdl-list] cosimulation trouble

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Jan Decaluwe wrote:
> 
>> Neal Becker wrote:
>>> Now I'm moving on to trying cosim.  I have installed icarus, compiled
>>> myhdl.vpi.  When run with normal sim result is fine, but when run as
>>> cosim I get no error, but nothing happens (I have a counter and an
>>> accumulator - the
>>> count never increments and the accumulator output never changes).  Any
>>> ideas?  Any hints at how to troubleshoot this?
>> Typically, the situation where "nothing happens" is caused by
>> initialization issues. In particular, in Verilog everything starts at 'X'
>> by default, while in MyHDL, the start value is defined.
>>
>> In this case, I guess count starts at 'X', and as it is not explicitly
>> reset, it stays at 'X'. Also, no events are generated to the MyHDL side,
>> so count seems to keep its starting value.
>>
>> The solution is to use an explicit reset signal that brings the circuit
>> into a known state.
>>
>> At the RTL level and higher, the MyHDL convertor could in fact generate
>> initialization values with the Verilog declarations to bring the Verilog
>> code more in line with MyHDL at time 0. The only reason why this isn't
>> done it that at one point it was reported that some synthesis tools
>> don't support that (I think it was the tool from Altera). I'm interested
>> in hearing whether that's still the case.
>>
>> At the gate level, you would always need the reset signal though.
>>
>> Jan
>>
> 
> I'm confused here.  count is both in and out from 'Counter'.  Counter is 
> instantiated in 'Decimator', which is instantiated in the top-level of 
> 'cosim'.  There, count is initialized to 0.  

When you do cosimulation, two simulators (MyHDL and Verilog) are running
in lockstep. The interface ports exist in the two simulators and their
values are kept consistent through events between the two simulators.

The problem you are seeing is probably due to 'count' in the *Verilog*
simulator. If it stays as X, nothing happens to 'count' in the MyHDL
simulator.

> What would I need to change?  

Consider a template with reset for RTL-level modeling:

http://www.myhdl.org/doc/0.6/manual/modeling.html#sequential-logic

> Why is it that in 'Counter' myhdl flags 'count' as output rather than inout?

An output that is used internally is not the same as a true inout. In Verilog,
it is not necessary to declare an inout in this case, but in VHDL it is.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] cosimulation trouble

[Neal B. <ndb...@gm...>]

I seem to have it working now.  I have restructured things a bit.  Perhaps 
someone might comment on whether the style here is good/reasonable.

from myhdl import Signal, always, intbv, Simulation, delay, toVerilog, 
traceSignals, always_comb, instance



def Counter (count, clock, n, reset):
    @always (clock.posedge)
    def cntLogic():
        if reset == 1:
            count.next = 0
        elif count == n-1:
            count.next = 0
        else:
            count.next = count + 1

#        print "count:", count
    return cntLogic

def accum (x, result, count, clock, n, reset):
    _sum = Signal (intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        if reset == 1:
            _sum.next = 0
        else:
            _sum.next = _sum + x
            if count == n-1:
                ##print 'count:', count, 'sum:', _sum
                result.next = _sum
                _sum.next = 0

    return accum_logic

def Decimator (clock, x, n, count, result, reset):
    cnt1 = Counter (count, clock, n, reset)
    acc1 = accum (x, result, count, clock, n, reset)
    return cnt1, acc1

def testbench(cosim=False):
    HALF_PERIOD = delay(1)

    clock = Signal (bool(0))
    x = Signal (intbv(0)[4:])
    reset = Signal (bool(1))
    count = Signal (intbv(0)[4:])
    result = Signal (intbv(0)[8:])
    n = 16
    
    if (cosim):
        from co import Decimator_v
        dut = Decimator_v (clock, x, n, count, result, reset)
    else:
        dut = Decimator (clock, x, n, count, result, reset)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    
    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            x.next = 1
            reset.next = 0
        
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'reset:', reset, 'x:', x, 'count:', count, 'result:', 
result

    return clockGen, stimulus, monitor, dut


def main():
    tb = traceSignals (testbench)

    Simulation(tb).run(50)

def cosim():
    tb = testbench(cosim=True)
    Simulation (tb).run (50)

mode = 'sim'
#mode = 'test'
#mode = 'cosim'
#mode = 'verilog'

if __name__ == '__main__':
     if mode == "sim":
        main()
    elif mode == "cosim":
        cosim()

co.py:
from myhdl import *
from test3 import Decimator
import os

def Decimator_v(clock, x, n, count, result, reset):
    toVerilog(Decimator, clock, x, n, count, result, reset)
    cmd = "iverilog -o Decimator tb_Decimator.v Decimator.v"
    os.system (cmd)
    
    return Cosimulation("vvp -v -m ./myhdl.vpi Decimator", **locals())