Thread: Re: [myhdl-list] new example for MyHDL, transciver is coming
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From: Xiang Li <u46...@an...> - 2009-05-19 10:31:48
Attachments:
uart_transciver.py
uart_transciver.v
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Hi all,<br><br>The new miniuart transciver file is coming along with its generated verilog file. Hopefully, you will like it<br><br>----- Original Message -----<br>From: Xiang Li <u46...@an...><br>Date: Monday, May 18, 2009 10:57 pm<br>Subject: [myhdl-list] new example for MyHDL<br>To: myh...@li...<br><br><font style="font-style: normal; font-weight: normal; background-color: rgb(245, 248, 240); font-size: 14px;">> </font>Hello all, I am a new user of MyHDL project. MyHDL is really a good project, which is ideal for software guys who are familiar with python and trying to do hardware development . I just wrote a miniuart project using MyHDL(rewrote from the source code downloaded from opencore website), for those novices who just come to the hardware world, it is a very good example for you. But if you are the experienced guys, then it might not be useful to you. This time I first attach one part of it, the receiver part source code and the generated verilog file, the others and document will be submitted in the next few days. > -----------------------------------------------------------------<br>> -------------<br>> Crystal Reports - New Free Runtime and 30 Day Trial<br>> Check out the new simplified licensing option that enables <br>> unlimited royalty-free distribution of the report engine <br>> for externally facing server and web deployment. <br>> http://p.sf.net/sfu/businessobjects> _______________________________________________<br>> myhdl-list mailing list<br>> myh...@li...<br>> https://lists.sourceforge.net/lists/listinfo/myhdl-list |
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From: Xiang Li <u46...@an...> - 2009-05-20 01:26:32
Attachments:
transciver.pdf
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Hi, <br><br>This time I add a rough structure diagram of transceiver of UART program for your reference. Hopefully, it will help you to understand the code of UART transceiver. <br><br>----- Original Message -----<br>From: Xiang Li <u46...@an...><br>Date: Monday, May 18, 2009 10:57 pm<br>Subject: [myhdl-list] new example for MyHDL<br>To: myh...@li...<br><br><font style="font-style: normal; font-weight: normal; background-color: rgb(245, 248, 240); font-size: 14px;">> </font>Hello all, I am a new user of MyHDL project. MyHDL is really a good project, which is ideal for software guys who are familiar with python and trying to do hardware development . I just wrote a miniuart project using MyHDL(rewrote from the source code downloaded from opencore website), for those novices who just come to the hardware world, it is a very good example for you. But if you are the experienced guys, then it might not be useful to you. This time I first attach one part of it, the receiver part source code and the generated verilog file, the others and document will be submitted in the next few days. > -----------------------------------------------------------------<br>> -------------<br>> Crystal Reports - New Free Runtime and 30 Day Trial<br>> Check out the new simplified licensing option that enables <br>> unlimited royalty-free distribution of the report engine <br>> for externally facing server and web deployment. <br>> http://p.sf.net/sfu/businessobjects> _______________________________________________<br>> myhdl-list mailing list<br>> myh...@li...<br>> https://lists.sourceforge.net/lists/listinfo/myhdl-list |
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From: Jose C. <jc...@gm...> - 2009-05-20 03:25:13
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On Tue, May 19, 2009 at 9:26 PM, Xiang Li <u46...@an...> wrote: > Hi, > > This time I add a rough structure diagram of transceiver of UART program > for your reference. Hopefully, it will help you to understand the code of > UART transceiver. > > ----- Original Message ----- > From: Xiang Li <u46...@an...> > Date: Monday, May 18, 2009 10:57 pm > Subject: [myhdl-list] new example for MyHDL > To: myh...@li... > > > Hello all, I am a new user of MyHDL project. MyHDL is really a good > project, which is ideal for software guys who are familiar with python and > trying to do hardware development . I just wrote a miniuart project using > MyHDL(rewrote from the source code downloaded from opencore website), for > those novices who just come to the hardware world, it is a very good example > for you. But if you are the experienced guys, then it might not be useful > to you. This time I first attach one part of it, the receiver part source > code and the generated verilog file, the others and document will be > submitted in the next few days. > > ----------------------------------------------------------------- > > ------------- > > Crystal Reports - New Free Runtime and 30 Day Trial > > Check out the new simplified licensing option that enables > > unlimited royalty-free distribution of the report engine > > for externally facing server and web deployment. > > http://p.sf.net/sfu/businessobjects> > _______________________________________________ > > myhdl-list mailing list > > myh...@li... > > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > ------------------------------------------------------------------------------ > Crystal Reports - New Free Runtime and 30 Day Trial > Check out the new simplified licensing option that enables > unlimited royalty-free distribution of the report engine > for externally facing server and web deployment. > http://p.sf.net/sfu/businessobjects > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > Nice diagram and it does help a lot more. Just curious, what software you use to generate those graphics? I've been trying to find a good free tool that does that, I've tried Dia but I don't like it very much. Thanks! |
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From: Xiang Li <u46...@an...> - 2009-05-20 12:04:05
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It is very simple. just use openoffice.org drawing tools is ok. ----- Original Message ----- From: Jose Cuello <jc...@gm...> Date: Wednesday, May 20, 2009 1:25 pm Subject: Re: [myhdl-list] new example for MyHDL, transciver diagram is coming To: General discussions on MyHDL <myh...@li...> > On Tue, May 19, 2009 at 9:26 PM, Xiang Li <u46...@an...> wrote: > Hi, > > This time I add a rough structure diagram of transceiver of UART program for your reference. Hopefully, it will help you to understand the code of UART transceiver. > > ----- Original Message ----- > From: Xiang Li <u46...@an...> > Date: Monday, May 18, 2009 10:57 pm > Subject: [myhdl-list] new example for MyHDL > To: myh...@li... > > > Hello all, I am a new user of MyHDL project. MyHDL is really a good project, which is ideal for software guys who are familiar with python and trying to do hardware development . I just wrote a miniuart project using MyHDL(rewrote from the source code downloaded from opencore website), for those novices who just come to the hardware world, it is a very good example for you. But if you are the experienced guys, then it might not be useful to you. This time I first attach one part of it, the receiver part source code and the generated verilog file, the others and document will be submitted in the next few days. > ----------------------------------------------------------------- > > ------------- > > Crystal Reports - New Free Runtime and 30 Day Trial > > Check out the new simplified licensing option that enables > > unlimited royalty-free distribution of the report engine > > for externally facing server and web deployment. > > http://p.sf.net/sfu/businessobjects> _______________________________________________ > > myhdl-list mailing list > > myh...@li... > > https://lists.sourceforge.net/lists/listinfo/myhdl-list > ------------------------------------------------------------------------------ > Crystal Reports - New Free Runtime and 30 Day Trial > Check out the new simplified licensing option that enables > unlimited royalty-free distribution of the report engine > for externally facing server and web deployment. > http://p.sf.net/sfu/businessobjects > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > > Nice diagram and it does help a lot more. Just curious, what software you use to generate those graphics? I've been trying to find a good free tool that does that, I've tried Dia but I don't like it very much. > > Thanks! > ----------------------------------------------------------------- > ------------- > Crystal Reports - New Free Runtime and 30 Day Trial > Check out the new simplified licensing option that enables > unlimited royalty-free distribution of the report engine > for externally facing server and web deployment. > http://p.sf.net/sfu/businessobjects> _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
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From: Xiang Li <u46...@an...> - 2009-05-20 14:27:49
Attachments:
receiver_timing.pdf
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The attachment is the timing diagram of receiver. From this small simple uart project, we can see that whether you are using verilog, VHDL or python to describe hardware, firstly, you should have hardware structure in your mind; secondly, timing diagram in your mind. <br><br>----- Original Message -----<br>From: Xiang Li <u46...@an...><br>Date: Monday, May 18, 2009 10:57 pm<br>Subject: [myhdl-list] new example for MyHDL<br>To: myh...@li...<br><br><font style="font-style: normal; font-weight: normal; background-color: rgb(245, 248, 240); font-size: 14px;">> </font>Hello all, I am a new user of MyHDL project. MyHDL is really a good project, which is ideal for software guys who are familiar with python and trying to do hardware development . I just wrote a miniuart project using MyHDL(rewrote from the source code downloaded from opencore website), for those novices who just come to the hardware world, it is a very good example for you. But if you are the experienced guys, then it might not be useful to you. This time I first attach one part of it, the receiver part source code and the generated verilog file, the others and document will be submitted in the next few days. > -----------------------------------------------------------------<br>> -------------<br>> Crystal Reports - New Free Runtime and 30 Day Trial<br>> Check out the new simplified licensing option that enables <br>> unlimited royalty-free distribution of the report engine <br>> for externally facing server and web deployment. <br>> http://p.sf.net/sfu/businessobjects> _______________________________________________<br>> myhdl-list mailing list<br>> myh...@li...<br>> https://lists.sourceforge.net/lists/listinfo/myhdl-list |
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