myhdl-list

[myhdl-list] Xilinx ISE and MyHDL

[Mike G. <zen...@ze...>]

Hi,

It is very attractive for the entire source code for a Xilinx ISE project to be 
managed in Python via myHDL. This needs Xilinx chip features like clock 
generators and RAM to be defined in Python. Is this possible, and what is the 
best approach?


Many thanks

Mike

Re: [myhdl-list] Xilinx ISE and MyHDL

[Jan D. <ja...@ja...>]

Mike Gill wrote:
> Hi,
> 
> It is very attractive for the entire source code for a Xilinx ISE project to be 
> managed in Python via myHDL. This needs Xilinx chip features like clock 
> generators and RAM to be defined in Python. Is this possible, and what is the 
> best approach?

In many cases, RAMs can be inferred from technology-independent
RTL code, which is the preferred approach if it works.

To instantiate technology-specific modules, you can use the
__verilog__ or __vhdl__ hook. For simulation purposes,
describe the functionality as usual. The convertor
will ignore that code and use the appopriate hook if it exists.

See:

http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Xilinx ISE and MyHDL

[Mike G. <zen...@ze...>]

Jan Decaluwe <jan <at> jandecaluwe.com> writes:

> 
> Mike Gill wrote:
> > Hi,
> > 
> > It is very attractive for the entire source code for a Xilinx ISE project 
to be 
> > managed in Python via myHDL. This needs Xilinx chip features like clock 
> > generators and RAM to be defined in Python. Is this possible, and what is 
the 
> > best approach?
> 
> In many cases, RAMs can be inferred from technology-independent
> RTL code, which is the preferred approach if it works.
> 
> To instantiate technology-specific modules, you can use the
> __verilog__ or __vhdl__ hook. For simulation purposes,
> describe the functionality as usual. The convertor
> will ignore that code and use the appopriate hook if it exists.
> 
> See:
> 
> http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
> 

Thanks for reply

Making ROM and distributed RAM is easy, but so far no luck with block RAM, and 
am afraid I can't work out from the manual section "User-Defined code" if and 
how to include a complete VHDL module such as made by an ISE wizard, or whether 
the code has to be copied and pasted, and in which case what (I am hoping MyHDL 
means not having to learn VHDL or Verilog in any detail)

I'd be grateful for an example. You seem to have a preference for Verilog - is 
this true?

MyHDL is a terrific idea, as is Python itself, but not many people are willing 
to strain their brains with new ideas, and need a lot of help and 
encouragement. How to use MyHDL in the design flow would help a lot, and 
examples of complete projects. DLP Design make a low cost Xilinx fpga module 
that is good for training, and it is easy to re-base their example projects on 
MyHDL (and talk to the module with a Python GUI)

The "flat" Verilog or VHDL file output means the ISE schematic has no useful 
hierarchy for complete designs. I find myself converting/synthesising 
individual blocks to see what each looks like, before assembling the whole 
design. MyHDL is a very fast approach and complicated stuff can be put together 
very quickly.

Regards

Mike

Re: [myhdl-list] Xilinx ISE and MyHDL

[Christopher F. <cf...@uc...>]

On Mon, Feb 22, 2010 at 9:42 AM, Mike Gill <zen...@ze...> wrote:

> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>
> >
> > Mike Gill wrote:
> > > Hi,
> > >
> > > It is very attractive for the entire source code for a Xilinx ISE
> project
> to be
> > > managed in Python via myHDL. This needs Xilinx chip features like clock
> > > generators and RAM to be defined in Python. Is this possible, and what
> is
> the
> > > best approach?
> >
> > In many cases, RAMs can be inferred from technology-independent
> > RTL code, which is the preferred approach if it works.
> >
> > To instantiate technology-specific modules, you can use the
> > __verilog__ or __vhdl__ hook. For simulation purposes,
> > describe the functionality as usual. The convertor
> > will ignore that code and use the appopriate hook if it exists.
> >
> > See:
> >
> > http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
> >
>
> Thanks for reply
>
> Making ROM and distributed RAM is easy, but so far no luck with block RAM,
> and
>

I think you will find that XST will determine, based on size, which to use
distributed or BRAM.  I have successfully inferred BRAM using the methods
Jan described.


> am afraid I can't work out from the manual section "User-Defined code" if
> and
> how to include a complete VHDL module such as made by an ISE wizard, or
> whether
> the code has to be copied and pasted, and in which case what (I am hoping
> MyHDL
> means not having to learn VHDL or Verilog in any detail)
>
> I'd be grateful for an example. You seem to have a preference for Verilog -
> is
> this true?
>

I don't think there is a preference for Verilog.  MyHDL is agnostic to which
HDL you convert to.  Many of the examples might be in Verilog because
Verilog was implemented first.  MyHDL was influenced by VHDL more than
Verilog.


>
> MyHDL is a terrific idea, as is Python itself, but not many people are
> willing
> to strain their brains with new ideas, and need a lot of help and
> encouragement. How to use MyHDL in the design flow would help a lot, and
> examples of complete projects. DLP Design make a low cost Xilinx fpga
> module
> that is good for training, and it is easy to re-base their example projects
> on
> MyHDL (and talk to the module with a Python GUI)
>

In the user and project areas there are many examples and projects.  If a
particular project or example is not clear or seems limited I think you will
get fast response if you post a specific questions to this mail group.  Me
personally, I use a top-level (very small) HDL (VHDL or Verilog)
to instantiate all vendor-hardware specific modules (
http://www.myhdl.org/doku.php/users:cfelton:projects:usbp).  I don't see any
drawback to this, all my work/development is in MyHDL.  All my simulation is
done with the MyHDL top-level.  I have had good success with MyHDL using a
variety of FPGA vendors.


>
> The "flat" Verilog or VHDL file output means the ISE schematic has no
> useful
> hierarchy for complete designs. I find myself converting/synthesising
> individual blocks to see what each looks like, before assembling the whole
> design. MyHDL is a very fast approach and complicated stuff can be put
> together
> very quickly.
>

Hmmm, not sure if you think this is a problem or it just an observation?


>
> Regards
>
> Mike
>
>
>
>
>
> ------------------------------------------------------------------------------
> Download Intel&#174; Parallel Studio Eval
> Try the new software tools for yourself. Speed compiling, find bugs
> proactively, and fine-tune applications for parallel performance.
> See why Intel Parallel Studio got high marks during beta.
> http://p.sf.net/sfu/intel-sw-dev
> _______________________________________________
> myhdl-list mailing list
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Xilinx ISE and MyHDL

[Jan D. <ja...@ja...>]

Mike Gill wrote:
> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
> 
>> Mike Gill wrote:
>>> Hi,
>>>
>>> It is very attractive for the entire source code for a Xilinx ISE project 
> to be 
>>> managed in Python via myHDL. This needs Xilinx chip features like clock 
>>> generators and RAM to be defined in Python. Is this possible, and what is 
> the 
>>> best approach?
>> In many cases, RAMs can be inferred from technology-independent
>> RTL code, which is the preferred approach if it works.
>>
>> To instantiate technology-specific modules, you can use the
>> __verilog__ or __vhdl__ hook. For simulation purposes,
>> describe the functionality as usual. The convertor
>> will ignore that code and use the appopriate hook if it exists.
>>
>> See:
>>
>> http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
>>
> 
> Thanks for reply
> 
> Making ROM and distributed RAM is easy, but so far no luck with block RAM, and 
> am afraid I can't work out from the manual section "User-Defined code" if and 
> how to include a complete VHDL module such as made by an ISE wizard, or whether 
> the code has to be copied and pasted, and in which case what (I am hoping MyHDL 
> means not having to learn VHDL or Verilog in any detail)

The only thing what you have to include is the VHDL or Verilog instantation of
the module. (The part about instantiation in VHDL or Verilog, you'll have to learn).

When your have made a macro, think about how you would instantiate that in
another Verilog or VHDL design. Paste such an instantiation into a string
assigned to __vhdl__ or __verilog__ in your MyHDL code.

The remaining thing is the way to attach MyHDL signals to the ports in your
instantiation. Instead of having actual Verilog or VHDL signal names in your
instantiation, you use Python format strings referring to MyHDL signals. E.g.
instead of "clock" you would use "%(clock). (I think this should be clear from
the examples, even though they don't show instantiations.)

Now after conversion, your code would contain the instantiation with the 
appropriate signals names filled in by the convertor.

Hope this helps?


> I'd be grateful for an example. You seem to have a preference for Verilog - is 
> this true?

Certainly not :-)

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Xilinx ISE and MyHDL

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Mike Gill wrote:
>> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>>
>>> Mike Gill wrote:
>>>> Hi,
>>>>
>>>> It is very attractive for the entire source code for a Xilinx ISE project 
>> to be 
>>>> managed in Python via myHDL. This needs Xilinx chip features like clock 
>>>> generators and RAM to be defined in Python. Is this possible, and what is 
>> the 
>>>> best approach?
>>> In many cases, RAMs can be inferred from technology-independent
>>> RTL code, which is the preferred approach if it works.
>>>
>>> To instantiate technology-specific modules, you can use the
>>> __verilog__ or __vhdl__ hook. For simulation purposes,
>>> describe the functionality as usual. The convertor
>>> will ignore that code and use the appopriate hook if it exists.
>>>
>>> See:
>>>
>>> http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
>>>
>> Thanks for reply
>>
>> Making ROM and distributed RAM is easy, but so far no luck with block RAM, and 
>> am afraid I can't work out from the manual section "User-Defined code" if and 
>> how to include a complete VHDL module such as made by an ISE wizard, or whether 
>> the code has to be copied and pasted, and in which case what (I am hoping MyHDL 
>> means not having to learn VHDL or Verilog in any detail)
> 
> The only thing what you have to include is the VHDL or Verilog instantation of
> the module. (The part about instantiation in VHDL or Verilog, you'll have to learn).
> 
> When your have made a macro, think about how you would instantiate that in
> another Verilog or VHDL design. Paste such an instantiation into a string
> assigned to __vhdl__ or __verilog__ in your MyHDL code.
> 
> The remaining thing is the way to attach MyHDL signals to the ports in your
> instantiation. Instead of having actual Verilog or VHDL signal names in your
> instantiation, you use Python format strings referring to MyHDL signals. E.g.
> instead of "clock" you would use "%(clock). (I think this should be clear from
> the examples, even though they don't show instantiations.)
> 
> Now after conversion, your code would contain the instantiation with the 
> appropriate signals names filled in by the convertor.
> 
> Hope this helps?

Let me add to my reply above that I was answering your question related
to user-defined code. I didn't intend to advocate that approach, certainly
not in this case.

As others have pointed out, I don't think user-defined code is the best option
for block ram. Back end tools should be able to infer that from a
technology-independent description.

Personally I would limit user-defined code for those cases were inference
by a synthesis tool or other back-end tools really isn't possible.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Xilinx ISE and MyHDL

[Kevin S. <sta...@gm...>]

I am surprised you can't get Xilinx ISE to instantiate Block RAM.  I am
very, very new to MyHDL and haven't done much yet other than follow the
tutorials, but I come from a strong VHDL background and have used all the
big FPGA vendors in projects: Xilinx, Altera, and Actel.

I have no problem getting Xilinx ISE to instantiate block ram with VHDL code
as simple as:

-- declaration of fifoMem
type FifoMemType is array(0 to DEPTH-1) of std_logic_vector(dataW'range);
signal fifoMem : FifoMemType;

-- code snippet of usage of fifoMem
process (clkW)
begin
  if (rising_edge(clkW)) then
    if (rstW = '1') then
      fifoMem <= (others => (others => '0'));
    else
      if (we = '1' and full = '0') then
        fifoMem(conv_integer(addrW'length-2 downto 0))) <= dataW;
      end if;
    end if;
  end if;
end process;

-- do something similar for a read.

So, you see, you can't just create an array of std_logic_vectors, and your
synthesis tool should pick out a Block RAM.  I use Synplify Pro (not XST) so
it is possible XST isn't as capable, but Synplify Pro seems to have no
problem mapping block ram to an RTL implementation of an async FIFO.

I would think that a MyHDL implementation of something similar should
produce synthesizable VHDL or Verilog that would properly map to a Block RAM
upon elaboration.

Can anyone with more MyHDL experience corroborate this?  If you could write
a working memory in MyHDL I could try synthesizing it in Synplify Pro to see
what happens...

Kevin

On Mon, Feb 22, 2010 at 9:42 AM, Mike Gill <zen...@ze...> wrote:

> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>
> >
> > Mike Gill wrote:
> > > Hi,
> > >
> > > It is very attractive for the entire source code for a Xilinx ISE
> project
> to be
> > > managed in Python via myHDL. This needs Xilinx chip features like clock
> > > generators and RAM to be defined in Python. Is this possible, and what
> is
> the
> > > best approach?
> >
> > In many cases, RAMs can be inferred from technology-independent
> > RTL code, which is the preferred approach if it works.
> >
> > To instantiate technology-specific modules, you can use the
> > __verilog__ or __vhdl__ hook. For simulation purposes,
> > describe the functionality as usual. The convertor
> > will ignore that code and use the appopriate hook if it exists.
> >
> > See:
> >
> > http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
> >
>
> Thanks for reply
>
> Making ROM and distributed RAM is easy, but so far no luck with block RAM,
> and
> am afraid I can't work out from the manual section "User-Defined code" if
> and
> how to include a complete VHDL module such as made by an ISE wizard, or
> whether
> the code has to be copied and pasted, and in which case what (I am hoping
> MyHDL
> means not having to learn VHDL or Verilog in any detail)
>
> I'd be grateful for an example. You seem to have a preference for Verilog -
> is
> this true?
>
> MyHDL is a terrific idea, as is Python itself, but not many people are
> willing
> to strain their brains with new ideas, and need a lot of help and
> encouragement. How to use MyHDL in the design flow would help a lot, and
> examples of complete projects. DLP Design make a low cost Xilinx fpga
> module
> that is good for training, and it is easy to re-base their example projects
> on
> MyHDL (and talk to the module with a Python GUI)
>
> The "flat" Verilog or VHDL file output means the ISE schematic has no
> useful
> hierarchy for complete designs. I find myself converting/synthesising
> individual blocks to see what each looks like, before assembling the whole
> design. MyHDL is a very fast approach and complicated stuff can be put
> together
> very quickly.
>
> Regards
>
> Mike
>
>
>
>
>
> ------------------------------------------------------------------------------
> Download Intel&#174; Parallel Studio Eval
> Try the new software tools for yourself. Speed compiling, find bugs
> proactively, and fine-tune applications for parallel performance.
> See why Intel Parallel Studio got high marks during beta.
> http://p.sf.net/sfu/intel-sw-dev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Kevin R. Stanton
c | 734•846•3915
e | sta...@gm...

Re: [myhdl-list] Xilinx ISE and MyHDL

[Christopher F. <chr...@gm...>]

Cross, posts, yes I can generate BRAM with ISE and Synplicity.  My
observations is the Synthesis tool (and map can modify) will determine based
on the size and routing which to use DRAM or BRAM.  If you wanted to force
the use of BRAM that might be a different issue.  But I think the question
can be asked, why force to BRAM?

.chris

On Mon, Feb 22, 2010 at 10:30 AM, Kevin Stanton <sta...@gm...> wrote:

> I am surprised you can't get Xilinx ISE to instantiate Block RAM.  I am
> very, very new to MyHDL and haven't done much yet other than follow the
> tutorials, but I come from a strong VHDL background and have used all the
> big FPGA vendors in projects: Xilinx, Altera, and Actel.
>
> I have no problem getting Xilinx ISE to instantiate block ram with VHDL
> code as simple as:
>
> -- declaration of fifoMem
> type FifoMemType is array(0 to DEPTH-1) of std_logic_vector(dataW'range);
> signal fifoMem : FifoMemType;
>
> -- code snippet of usage of fifoMem
> process (clkW)
> begin
>   if (rising_edge(clkW)) then
>     if (rstW = '1') then
>       fifoMem <= (others => (others => '0'));
>     else
>       if (we = '1' and full = '0') then
>         fifoMem(conv_integer(addrW'length-2 downto 0))) <= dataW;
>       end if;
>     end if;
>   end if;
> end process;
>
> -- do something similar for a read.
>
> So, you see, you can't just create an array of std_logic_vectors, and your
> synthesis tool should pick out a Block RAM.  I use Synplify Pro (not XST) so
> it is possible XST isn't as capable, but Synplify Pro seems to have no
> problem mapping block ram to an RTL implementation of an async FIFO.
>
> I would think that a MyHDL implementation of something similar should
> produce synthesizable VHDL or Verilog that would properly map to a Block RAM
> upon elaboration.
>
> Can anyone with more MyHDL experience corroborate this?  If you could write
> a working memory in MyHDL I could try synthesizing it in Synplify Pro to see
> what happens...
>
> Kevin
>
>
> On Mon, Feb 22, 2010 at 9:42 AM, Mike Gill <zen...@ze...> wrote:
>
>> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>>
>> >
>> > Mike Gill wrote:
>> > > Hi,
>> > >
>> > > It is very attractive for the entire source code for a Xilinx ISE
>> project
>> to be
>> > > managed in Python via myHDL. This needs Xilinx chip features like
>> clock
>> > > generators and RAM to be defined in Python. Is this possible, and what
>> is
>> the
>> > > best approach?
>> >
>> > In many cases, RAMs can be inferred from technology-independent
>> > RTL code, which is the preferred approach if it works.
>> >
>> > To instantiate technology-specific modules, you can use the
>> > __verilog__ or __vhdl__ hook. For simulation purposes,
>> > describe the functionality as usual. The convertor
>> > will ignore that code and use the appopriate hook if it exists.
>> >
>> > See:
>> >
>> > http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
>> >
>>
>> Thanks for reply
>>
>> Making ROM and distributed RAM is easy, but so far no luck with block RAM,
>> and
>> am afraid I can't work out from the manual section "User-Defined code" if
>> and
>> how to include a complete VHDL module such as made by an ISE wizard, or
>> whether
>> the code has to be copied and pasted, and in which case what (I am hoping
>> MyHDL
>> means not having to learn VHDL or Verilog in any detail)
>>
>> I'd be grateful for an example. You seem to have a preference for Verilog
>> - is
>> this true?
>>
>> MyHDL is a terrific idea, as is Python itself, but not many people are
>> willing
>> to strain their brains with new ideas, and need a lot of help and
>> encouragement. How to use MyHDL in the design flow would help a lot, and
>> examples of complete projects. DLP Design make a low cost Xilinx fpga
>> module
>> that is good for training, and it is easy to re-base their example
>> projects on
>> MyHDL (and talk to the module with a Python GUI)
>>
>> The "flat" Verilog or VHDL file output means the ISE schematic has no
>> useful
>> hierarchy for complete designs. I find myself converting/synthesising
>> individual blocks to see what each looks like, before assembling the whole
>> design. MyHDL is a very fast approach and complicated stuff can be put
>> together
>> very quickly.
>>
>> Regards
>>
>> Mike
>>
>>
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Download Intel&#174; Parallel Studio Eval
>> Try the new software tools for yourself. Speed compiling, find bugs
>> proactively, and fine-tune applications for parallel performance.
>> See why Intel Parallel Studio got high marks during beta.
>> http://p.sf.net/sfu/intel-sw-dev
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
> Kevin R. Stanton
> c | 734•846•3915
> e | sta...@gm...
>
>
> ------------------------------------------------------------------------------
> Download Intel&#174; Parallel Studio Eval
> Try the new software tools for yourself. Speed compiling, find bugs
> proactively, and fine-tune applications for parallel performance.
> See why Intel Parallel Studio got high marks during beta.
> http://p.sf.net/sfu/intel-sw-dev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>