Thread: [myhdl-list] signed bit vectors
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From: Matt E. <ma...@et...> - 2005-10-25 06:17:26
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I just discovered MyHDL today, and it appears to be just what I've been looking for! Thanks for making it and for documenting it so well! I was able to get up and running with complex simulations in less than half a day. I just have a couple of questions -- Is there any way to make intbv's signed? Also, how do I specify the bitwidth? Thanks, Matt |
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From: nicran <ni...@gm...> - 2005-10-25 07:27:12
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As I know, there is no way to specify the bitwidth, you can only specify the default value of a bitvector. 2005/10/25, Matt Ettus <ma...@et...>: > I just discovered MyHDL today, and it appears to be just what I've been > looking for! Thanks for making it and for documenting it so well! I > was able to get up and running with complex simulations in less than > half a day. > > I just have a couple of questions -- Is there any way to make intbv's > signed? Also, how do I specify the bitwidth? > > Thanks, > Matt > > > ------------------------------------------------------- > This SF.Net email is sponsored by the JBoss Inc. > Get Certified Today * Register for a JBoss Training Course > Free Certification Exam for All Training Attendees Through End of 2005 > Visit http://www.jboss.com/services/certification for more information > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > |
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From: David B. <dav...@fr...> - 2005-10-25 07:41:43
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Yes you can: http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-intbv.html David. Selon nicran <ni...@gm...>: > As I know, there is no way to specify the bitwidth, you can only > specify the default value of a bitvector. > > > 2005/10/25, Matt Ettus <ma...@et...>: > > I just discovered MyHDL today, and it appears to be just what I've be= en > > looking for! Thanks for making it and for documenting it so well! I > > was able to get up and running with complex simulations in less than > > half a day. > > > > I just have a couple of questions -- Is there any way to make intbv's > > signed? Also, how do I specify the bitwidth? > > > > Thanks, > > Matt > > > > > > ------------------------------------------------------- > > This SF.Net email is sponsored by the JBoss Inc. > > Get Certified Today * Register for a JBoss Training Course > > Free Certification Exam for All Training Attendees Through End of 200= 5 > > Visit http://www.jboss.com/services/certification for more informatio= n > > _______________________________________________ > > myhdl-list mailing list > > myh...@li... > > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > > > > ------------------------------------------------------- > This SF.Net email is sponsored by the JBoss Inc. > Get Certified Today * Register for a JBoss Training Course > Free Certification Exam for All Training Attendees Through End of 2005 > Visit http://www.jboss.com/services/certification for more information > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > |
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From: Matt E. <ma...@et...> - 2005-10-25 07:52:43
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David Brochart wrote: > Yes you can: > > http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-intbv.html > Do you mean that the bitwidth is specified implicitly through the min and max? Matt |
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From: David B. <dav...@fr...> - 2005-10-25 08:27:12
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Yes, but you can also specify the range explicitly: s =3D Signal(intbv(0)[m : n]) s would be a std_logic_vector(m - 1 downto n) in VHDL. David. Selon Matt Ettus <ma...@et...>: > David Brochart wrote: > > Yes you can: > > > > http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-intbv.html > > > > Do you mean that the bitwidth is specified implicitly through the min > and max? > > Matt > > > ------------------------------------------------------- > This SF.Net email is sponsored by the JBoss Inc. > Get Certified Today * Register for a JBoss Training Course > Free Certification Exam for All Training Attendees Through End of 2005 > Visit http://www.jboss.com/services/certification for more information > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > |
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From: Jan D. <ja...@ja...> - 2005-10-26 20:30:25
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David Brochart wrote:
> Yes, but you can also specify the range explicitly:
>
> s = Signal(intbv(0)[m : n])
>
> s would be a std_logic_vector(m - 1 downto n) in VHDL.
Actually, it's more like std_logic_vector(m-n-1 downto 0). However, the
typical usage pattern in this case would be with n=0.
I thought it was useful to add a FAQ entry for the original question:
http://myhdl.jandecaluwe.com/doku.php/faq
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Electronic design with Python:
http://myhdl.jandecaluwe.com
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From: Matt E. <ma...@et...> - 2005-10-25 07:42:34
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nicran wrote: > As I know, there is no way to specify the bitwidth, you can only > specify the default value of a bitvector. > > > 2005/10/25, Matt Ettus <ma...@et...>: > >>I just discovered MyHDL today, and it appears to be just what I've been >>looking for! Thanks for making it and for documenting it so well! I >>was able to get up and running with complex simulations in less than >>half a day. >> >>I just have a couple of questions -- Is there any way to make intbv's >>signed? Also, how do I specify the bitwidth? I just found how to set ranges, which is I guess the substitute for setting bitwidths. However, when I set an intbv signal to a negative value, it is giving me X's in my verilog simulation. Any ideas? Thanks, Matt |
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From: Tom D. <td...@di...> - 2005-10-25 14:01:29
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Matt, The current version of toVerilog does not support signed numbers. It is in the works for the next release. Check out the new features: http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5 Tom Matt Ettus wrote: >nicran wrote: > > >>As I know, there is no way to specify the bitwidth, you can only >>specify the default value of a bitvector. >> >> >>2005/10/25, Matt Ettus <ma...@et...>: >> >> >> >>>I just discovered MyHDL today, and it appears to be just what I've been >>>looking for! Thanks for making it and for documenting it so well! I >>>was able to get up and running with complex simulations in less than >>>half a day. >>> >>>I just have a couple of questions -- Is there any way to make intbv's >>>signed? Also, how do I specify the bitwidth? >>> >>> > >I just found how to set ranges, which is I guess the substitute for >setting bitwidths. However, when I set an intbv signal to a negative >value, it is giving me X's in my verilog simulation. > >Any ideas? > >Thanks, >Matt > > >------------------------------------------------------- >This SF.Net email is sponsored by the JBoss Inc. >Get Certified Today * Register for a JBoss Training Course >Free Certification Exam for All Training Attendees Through End of 2005 >Visit http://www.jboss.com/services/certification for more information >_______________________________________________ >myhdl-list mailing list >myh...@li... >https://lists.sourceforge.net/lists/listinfo/myhdl-list > > > |
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From: Matt E. <ma...@et...> - 2005-10-25 18:46:20
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Tom Dillon wrote: > Matt, > > The current version of toVerilog does not support signed numbers. > > It is in the works for the next release. Check out the new features: > > http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5 I'm not using toVerilog. I am doing cosimulation with icarus, and negative numbers I send into the verilog side have x's in them (but not all the bits, just the upper ones). Matt |
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From: Tom D. <td...@di...> - 2005-10-25 22:29:06
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Matt, There are also a couple of changes required to _Cosimulation.py to pass the numbers properly. I can send you my hacked version if you like. Tom Matt Ettus wrote: >Tom Dillon wrote: > > >>Matt, >> >>The current version of toVerilog does not support signed numbers. >> >>It is in the works for the next release. Check out the new features: >> >>http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5 >> >> > > >I'm not using toVerilog. I am doing cosimulation with icarus, and >negative numbers I send into the verilog side have x's in them (but not >all the bits, just the upper ones). > >Matt > > >------------------------------------------------------- >This SF.Net email is sponsored by the JBoss Inc. >Get Certified Today * Register for a JBoss Training Course >Free Certification Exam for All Training Attendees Through End of 2005 >Visit http://www.jboss.com/services/certification for more information >_______________________________________________ >myhdl-list mailing list >myh...@li... >https://lists.sourceforge.net/lists/listinfo/myhdl-list > > > |
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From: Matt E. <ma...@et...> - 2005-10-25 22:35:16
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Tom Dillon wrote: > Matt, > > There are also a couple of changes required to _Cosimulation.py to pass > the numbers properly. > > I can send you my hacked version if you like. That would be a wonderful help, thanks! Matt |
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From: Jan D. <ja...@ja...> - 2005-10-26 20:54:47
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Matt Ettus wrote: > Tom Dillon wrote: > >>Matt, >> >>The current version of toVerilog does not support signed numbers. >> >>It is in the works for the next release. Check out the new features: >> >>http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5 > > > > I'm not using toVerilog. I am doing cosimulation with icarus, and > negative numbers I send into the verilog side have x's in them (but not > all the bits, just the upper ones). As it happens, I am working on signed support for Verilog currently. It was not yet supported for Verilog conversion (documented) and for co-simulation (undocumented - don't know why). I deferred this because I thought it would be tricky. It is! (at the Verilog side). I have found that Icarus is buggy with respect to signed support. See: http://groups.google.be/groups?q=Verilog+signed+arithmetic+Decaluwe "Buggy" simply means that it doesn't what other Verilog simulators, including the big ones, do. I am relying on Cver for this now. Development version 0.5dev2 has Verilog co-simulation support for negative intbv's (I need this to verify the Verilog conversion work). Regards, Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium Electronic design with Python: http://myhdl.jandecaluwe.com |
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