Hello everyone,
this is my first post to this list. I also posted this question on
comp.lang.verilog and comp.lang.vhdl as a 'reply' to the message on the
first ASIC designed with myHDL (great news!).
This list is probably more appropriate for posting my question, so here
goes. The rest of this message is a copy of the text also posted to the
newsgroups:
Hello Jan,
First of all, congratulations with this result!
I have only recently become acquainted with myHDL and it looks very
nice.
Specifically, I like myHDL's conversion capabilities and the
possibility of writing testbenches in python.
I have a question on myHDL's conversion capabilities:
When I use a 'elif some_condition:' statement and try to translate it
to VHDL I get the following error:
myhdl.ConversionError: in file regp2p.py, line 15:
no else test
With the toVerilog function the translation works fine.
Is a 'elif some_condition:' statement treated differently by the
toVHDL function (than by the toVerilog function) or is a 'elif
some_condition:' statement in myHDL something other than a 'else: if
some_condition:' statement?
I attached a small example at the end of this post (a posedge
sensitive register with an asynchronous clear and an enable input).
Thanks,
Patrick
from myhdl import *
def regp2p(
clr,
clk,
en,
pin,
pout,
width
):
intreg = Signal(intbv(0)[width:])
@always(clk.posedge, clr.posedge)
def register_p2p():
if clr:
intreg.next = 0
# This works with toVerilog but not with toVHDL
elif en:
intreg.next = pin
# This works with both toVerilog and toVHDL
# else:
# if en:
# intreg.next = pin
@always_comb
def outputs():
pout.next = intreg
return register_p2p, outputs
width = int(8)
clr = Signal(bool(0))
clk = Signal(bool(0))
en = Signal(bool(0))
pin = Signal(intbv(0)[width:])
pout = Signal(intbv(0)[width:])
def main():
toVerilog.name = 'regp2p'
toVerilog(
regp2p,
clr = clr,
clk = clk,
en = en,
pin = pin,
pout = pout,
width = width
)
toVHDL(
regp2p,
clr = clr,
clk = clk,
en = en,
pin = pin,
pout = pout,
width = width
)
if __name__ == '__main__':
main()
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