myhdl-list

[myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

Hi all,

   I'm gettin' hungry to do some more FPGA stuff again. Could anyone give
me some pointers on how a tristate data bus could be implemented in
myHDL?

Thanks,
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

>
> Hi all,
>
>    I'm gettin' hungry to do some more FPGA stuff again. Could anyone gi=
ve
> me some pointers on how a tristate data bus could be implemented in
> myHDL?
>

     Maybe I should be more clear. I'm looking to create a *bidirectional=
*
bus to an external SRAM chip. I suppose somehow the output driver
needs to get tristated when the the bus is in input mode. I'm not
sure how to bring this about, or if the fpga software tool will infer
this for me, etc.

Any advice would be great!

Thanks

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>Hi all,
>>
>>   I'm gettin' hungry to do some more FPGA stuff again. Could anyone give
>>me some pointers on how a tristate data bus could be implemented in
>>myHDL?
>>
> 
> 
>      Maybe I should be more clear. I'm looking to create a *bidirectional*
> bus to an external SRAM chip. I suppose somehow the output driver
> needs to get tristated when the the bus is in input mode. I'm not
> sure how to bring this about, or if the fpga software tool will infer
> this for me, etc.
> 
> Any advice would be great!

I've deliberately neglected the issue because I believe there's
hardly a good reason to use tristates *on-chip*.

But you are talking about off-chip of course. Let's separate
the issues:

Modeling
--------

In 0.5 it is possible to use None as a value for an intbv:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#backwards_incompatible_changes

The idea is to use None to represent a tristate value. I believe this
is quite appropriate.

When you use a None value in an expression, you will easily get
tracebacks. Also this I think is appropriate. In other words,
I don't plan to extend operator support for intbv's to do something
"meaningful" with None values. The designer should surround such
expressions with tests for appropriate usage. (E.g. note that
any value is larger than None in Python.)

Verilog conversion support
--------------------------

Nothing has been done. At least 2 things would be needed:
1) convert a None constant value to 'Z'
2) infer inout ports at the top-level interface when
an interface signal is used as such.

In addition, it would be nice to know what templates are
exactly supported by the mainstream fgpa synthesis tools
to infer tristates, tristate ports, and bidirectional ports.
This may influence Verilog conversion choices.

Because of 2), you cannot simply use the user-defined verilog
feature to specify the verilog code you want yourself.
I fear the workaround at this point is a manually written
top-level Verilog wrapper, as suggested elsewhere.

For a possible implementation of the features discussed
above, I need feedback from users to find out and specify
exactly what needs to be done, and how urgent it is.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

>>      Maybe I should be more clear. I'm looking to create a
>> *bidirectional*
>> bus to an external SRAM chip. I suppose somehow the output driver
>> needs to get tristated when the the bus is in input mode. I'm not
>> sure how to bring this about, or if the fpga software tool will infer
>> this for me, etc.

> But you are talking about off-chip of course. Let's separate
> the issues:

> Verilog conversion support
> --------------------------
>
> Nothing has been done. At least 2 things would be needed:
> 1) convert a None constant value to 'Z'
> 2) infer inout ports at the top-level interface when
> an interface signal is used as such.
>
> In addition, it would be nice to know what templates are
> exactly supported by the mainstream fgpa synthesis tools
> to infer tristates, tristate ports, and bidirectional ports.
> This may influence Verilog conversion choices.
>
> Because of 2), you cannot simply use the user-defined verilog
> feature to specify the verilog code you want yourself.
> I fear the workaround at this point is a manually written
> top-level Verilog wrapper, as suggested elsewhere.
>

Great to hear from you again Jan!

I will try out your and Gunter's suggestions. What I'd like is an
automatic way to combine the myhdl code with a user-supplied top-level
Verilog wrapper.

This might be doable with shell scripting and/or make, but being able to
specify the wrapper filename inside the myHDL code sounds like a better
way right now. MyHDL could automatically incorporate the wrapper into its
Verilog output. I'll have to experiment a bit to be sure, but what do you
think?

> For a possible implementation of the features discussed
> above, I need feedback from users to find out and specify
> exactly what needs to be done, and how urgent it is.
>

I'll be glad to give you any feedback I can. I'm starting to create a VGA
controller in my FPGA, and in a while, I'll need to access external RAM :=
)

Peace,

George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> Great to hear from you again Jan!

As from you. I notice that many people find their way to the MyHDL
pages from your fpga synth project (although not many seem to
follow your path and go for it themselves :-). What are you
doing with this project - do you share it with other enthousiast?
Plans to open source it? or commercial plans?

> I will try out your and Gunter's suggestions. What I'd like is an
> automatic way to combine the myhdl code with a user-supplied top-level
> Verilog wrapper.
> 
> This might be doable with shell scripting and/or make, but being able to
> specify the wrapper filename inside the myHDL code sounds like a better
> way right now. MyHDL could automatically incorporate the wrapper into its
> Verilog output. I'll have to experiment a bit to be sure, but what do you
> think?

At some point I would like to take some time to think thorougly
about tristates and inouts and come up with a satisfactory
solution, hopefully based on user inputs and feedback.
Currently, I'm focussed on getting toVHDL on track
and right - which offers more than enough brain teasers :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> Great to hear from you again Jan!

As from you. I notice that many people find their way to the MyHDL
pages from your fpga synth project (although not many seem to
follow your path and go for it themselves :-). What are you
doing with this project - do you share it with other enthousiast?
Plans to open source it? or commercial plans?

> I will try out your and Gunter's suggestions. What I'd like is an
> automatic way to combine the myhdl code with a user-supplied top-level
> Verilog wrapper.
> 
> This might be doable with shell scripting and/or make, but being able to
> specify the wrapper filename inside the myHDL code sounds like a better
> way right now. MyHDL could automatically incorporate the wrapper into its
> Verilog output. I'll have to experiment a bit to be sure, but what do you
> think?

At some point I would like to take some time to think thorougly
about tristates and inouts and come up with a satisfactory
solution, hopefully based on user inputs and feedback.
Currently, I'm focussed on getting toVHDL on track
and right - which offers more than enough brain teasers :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

> As from you. I notice that many people find their way to the MyHDL
> pages from your fpga synth project (although not many seem to
> follow your path and go for it themselves :-). What are you
> doing with this project - do you share it with other enthousiast?
> Plans to open source it? or commercial plans?
>   
:-) They don't know what they're missing.. Python and MyHDL rock!

I'm not sure yet what I want to do. I might open source some version, 
and I have had several people ask me if I will sell it. That's a 
possibility. But for a next step, I'd really like to get a board made. 
I've designed boards before, and I miss it.. its hard, exacting work, 
but its also fun and so cool being able to hold this complicated looking 
board in your hand and say "hey, I made this!"


>
> At some point I would like to take some time to think thorougly
> about tristates and inouts and come up with a satisfactory
> solution, hopefully based on user inputs and feedback.
> Currently, I'm focussed on getting toVHDL on track
> and right - which offers more than enough brain teasers :-)
>
>   
Wow, so toVHDL is alive. I thought we didn't need it :) I'm sure you 
have a good reason for pursuing it though.


By the way, I set up subversion for version control and have started to 
build my own library of reusable parts. I'm so glad I took the time to 
set this all up, its helping me get back and enjoy it even more this 
time around!

Regards,
George

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> 
> Wow, so toVHDL is alive. I thought we didn't need it :)

Me too. But that was 2 years ago :-)

I have changed my mind because of the following reasons.

First, from the feedback I got it is clear that VHDL is
more popular than I anticipated, especially in the FPGA
world. Naturally, a tool has more chance of adoption if
it plays well with existing design flows.

A related second reason is that having both Verilog and
VHDL output from a single source creates a capability
that is afaik unique: designing IP blocks once and
creating equivalent RTL-level Verilog and VHDL automatically.
That must be an attractive proposition to IP developers.

Third, I found a way to solve the issue of how to verify
the VHDL output without need for co-simulation. I'm using
a prototype of this currently - works great.

And fourth, it was time for a new intellecual challenge :-)

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Python 2.5 released!

[George P. <ge...@ga...>]

A brand new version of my favorite programming language is out, Python 2.=
5:

http://www.python.org/news/

New with Python 2.5 is an interesting new capability of passing values
into generators:

http://docs.python.org/dev/whatsnew/pep-342.html

Can this make it possible for @always and @instance blocks to have local
variables?

Rock on,

George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

> At some point I would like to take some time to think thorougly
> about tristates and inouts and come up with a satisfactory
> solution, hopefully based on user inputs and feedback.
> Currently, I'm focussed on getting toVHDL on track
> and right - which offers more than enough brain teasers :-)
>
>   
Hi Jan,

Looks like you've been on a roll with toVHDL! I'm looking forward to 
trying out 0.6dev3 with its signed support.

I'm planning a HD44780-based LCD interface for the growing MyHDL IP 
library. I think this is a necessary and useful addition with a lot of 
popular appeal. To achieve my design goals, I'll need some 
bidirectional/tristate support. How's that coming along? :-) Can I help 
somehow?

Thanks,
George

> Jan
>
>   

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>At some point I would like to take some time to think thorougly
>>about tristates and inouts and come up with a satisfactory
>>solution, hopefully based on user inputs and feedback.
>>Currently, I'm focussed on getting toVHDL on track
>>and right - which offers more than enough brain teasers :-)
>>
>>  
> 
> Hi Jan,
> 
> Looks like you've been on a roll with toVHDL! I'm looking forward to 
> trying out 0.6dev3 with its signed support.

It's available now.

> 
> I'm planning a HD44780-based LCD interface for the growing MyHDL IP 
> library. I think this is a necessary and useful addition with a lot of 
> popular appeal. To achieve my design goals, I'll need some 
> bidirectional/tristate support. How's that coming along? :-) Can I help 
> somehow?

I'll no longer try to release 0.6 before the year-end. Instead,
with 0.6dev3 out I now want to make some progress with myhdl.org,
so that it is up and running and stable before 0.6. After that,
I promise I'll look into the bidir/tristate functionality. I'm
sure you'll be able to help but I want to do it right and it
will take some time. I may decide to include it in 0.6.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

On Wed, December 13, 2006 9:16 am, Jan Decaluwe wrote:
> George Pantazopoulos wrote:
>>>At some point I would like to take some time to think thorougly
>>>about tristates and inouts and come up with a satisfactory
>>>solution, hopefully based on user inputs and feedback.
>>>Currently, I'm focussed on getting toVHDL on track
>>>and right - which offers more than enough brain teasers :-)
>>>
>>>
>>
>> Hi Jan,
>>
>> Looks like you've been on a roll with toVHDL! I'm looking forward to
>> trying out 0.6dev3 with its signed support.
>
> It's available now.
>
>>
>> I'm planning a HD44780-based LCD interface for the growing MyHDL IP
>> library. I think this is a necessary and useful addition with a lot of
>> popular appeal. To achieve my design goals, I'll need some
>> bidirectional/tristate support. How's that coming along? :-) Can I hel=
p
>> somehow?
>
> I'll no longer try to release 0.6 before the year-end. Instead,
> with 0.6dev3 out I now want to make some progress with myhdl.org,
> so that it is up and running and stable before 0.6. After that,
> I promise I'll look into the bidir/tristate functionality. I'm
> sure you'll be able to help but I want to do it right and it
> will take some time. I may decide to include it in 0.6.
>
> Jan
>

Thanks Jan, I appreciate your effort, as always. No rush on the Tristate
support. I've been busy, but I plan on getting back into my electronic
design stuff between xmas and new years. Feel free to ask for
help/feedback.

Regards,
George

http://www.gammaburst.net

Re: [myhdl-list] Tristate bus to external SRAM

[Randy L. <Dog...@bl...>]

George Pantazopoulos <george <at> gammaburst.net> writes:

> 
> 
> On Wed, December 13, 2006 9:16 am, Jan Decaluwe wrote:
> > George Pantazopoulos wrote:
> >>>At some point I would like to take some time to think thorougly
> >>>about tristates and inouts and come up with a satisfactory
> >>>solution, hopefully based on user inputs and feedback.
> >>>Currently, I'm focussed on getting toVHDL on track
> >>>and right - which offers more than enough brain teasers 



Thanks for all the work on MyHDL.

The project I'm looking at requires Tri-state signals for external 8-bit data
path to memory. I noticed that the latest dev release (0.6dev4) includes
Tri-state support for simulation. I have installed dev4, all of the examples
run, but I am having difficulty using the Tri-state signals. I have a lot of
experience in Python, none with MyHDL.

Is the dev4 release stable enough to use for simulation?

Is the Tri-state signal working?

If yes, could you post a simple example of using a Tri-state signal?

Thanks again. 

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

Randy Lea wrote:

> Thanks for all the work on MyHDL.

Thanks for the interest.

> The project I'm looking at requires Tri-state signals for external 8-bit data
> path to memory. I noticed that the latest dev release (0.6dev4) includes
> Tri-state support for simulation. I have installed dev4, all of the examples
> run, but I am having difficulty using the Tri-state signals. I have a lot of
> experience in Python, none with MyHDL.
> 
> Is the dev4 release stable enough to use for simulation?

In general, for all features in earlier releases (1.5.1) it should be stable or
better because of bug fixes. Features under development will be buggy
or incomplete.

> Is the Tri-state signal working?

There is in an experimental implementation (corresponding to MEP 103)
in 0.6dev4. No extensive testing or unit tests yet though.

> If yes, could you post a simple example of using a Tri-state signal?

Sure. Here is the example that I used to quickly check the experimental
implementation. Let me know if this functionality is what you're looking
for:

---
from myhdl import *

def test(bus):

     d1 = bus.driver()
     d2 = bus.driver()
     d3 = bus.driver()

     @instance
     def proc1():

         for v in (1, None, 2, None, 3, 10, None, None):
             yield delay(10)
             d1.next = v

         raise StopSimulation

     @instance
     def proc2():

         for v in (None, 4, None, 5, 6, None, None):
             yield delay(10)
             d2.next = v

     @instance
     def proc3():
         for v in (None, None, None, None, None, None, 44):
             yield delay(10)
             d3.next = v

     @always(bus)
     def monitor():
         print now(), bus

     return proc1, proc2, proc3, monitor

bus = Tristate(intbv(0)[4:])
sim = Simulation(test(bus))
sim.run()

---
Output:

 > python test.py
10 1
20 4
30 2
40 5
** BusContentionWarning: Bus contention
** BusContentionWarning: Bus contention
** BusContentionWarning: Bus contention
50 None
60 10
70 44
---

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Tristate bus to external SRAM

[Guenter D. <dan...@we...>]

George Pantazopoulos wrote:
>> Hi all,
>>
>>    I'm gettin' hungry to do some more FPGA stuff again. Could anyone give
>> me some pointers on how a tristate data bus could be implemented in
>> myHDL?
>>
> 
>      Maybe I should be more clear. I'm looking to create a *bidirectional*
> bus to an external SRAM chip. I suppose somehow the output driver
> needs to get tristated when the the bus is in input mode. I'm not
> sure how to bring this about, or if the fpga software tool will infer
> this for me, etc.
> 

You could try doing a multiplexer in Verilog and interface that to your
Python code. Something like this:

      MyHDL       |       Verilog
                  |
                       +\
      Write data ----->+ \
                       |  +<----->
      Read data  <-----+ /
                       +/
                  |


You would also need a control signal to specify the direction.

Maybe that works?

Cheers,

Guenter

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

>>
>>      Maybe I should be more clear. I'm looking to create a
>> *bidirectional*
>> bus to an external SRAM chip. I suppose somehow the output driver
>> needs to get tristated when the the bus is in input mode. I'm not
>> sure how to bring this about, or if the fpga software tool will infer
>> this for me, etc.
>>
>
> You could try doing a multiplexer in Verilog and interface that to your
> Python code. Something like this:
>
>       MyHDL       |       Verilog
>                   |
>                        +\
>       Write data ----->+ \
>                        |  +<----->
>       Read data  <-----+ /
>                        +/
>                   |

I'll check that out, thanks. I also came across a verilog tutorial for
bidirectional/tristate here:
http://www.quicklogic.com/images/quicknote36.pdf#search=3D%22verilog%20tr=
istate%22

module example (OE, in1, in2, bi_ext, tri_ext);
input OE, in1, in2;
inout bi_ext;
output tri_ext;
wire bi_ext =3D OE ? (in1 & in2) : 1=92bz;
wire tri_ext =3D OE ? (bi_ext | in2) : 1=92bz;
endmodule

So between those two I think I can get something to work. Any tips on how
to smoothly integrate this with myHDL?

Thanks,

--=20
George Pantazopoulos
http://www.gammaburst.net