myhdl-list

[myhdl-list] List of Signals as input/output in a toVerilog()

[Jens P. A. <je...@if...>]

Hi.

I've been experimenting much with MyHDL, I like it, and I'd like to make  
some synthesizeable code real soon. I don't have any Verilog/VHDL  
experience, maybe my questions are very basic.

All the examples I've seen of MyHDL->Verilog has a set number of  
input/output signals. I'd like to create a program which has all the  
signals inside a list (to be more flexible).

Consider the following example:

def make_many_sregs(clk,din,WIDTH,out,reset,enable,NR_REGS):
     inst = [shiftreg(clk,din[i],WIDTH,out[i],reset,enable) for i in  
range(NR_REGS)]
     return inst

def convert_shiftregister_to_verilog():
     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
     WIDTH=8
     NR_REGS=2
     out = [Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
     din = [Signal(bool(0)) for i in range(NR_REGS)]

     toVerilog.name="shiftregister"
     toVerilog(make_many_sregs,clk,din,WIDTH,out,reset,enable,NR_REGS)

The intention is that NR_REGS gives how many shift-registers I'd like. I  
make the same number of data in and parallel out Signals as  
shift-registers.
This is the generated Verilog code. Where are din/out signals?

module shiftregister (
     clk,
     reset,
     enable
);

input clk;
input reset;
input enable;

wire _inst_2_din;
reg [7:0] _inst_2_pout;
reg [7:0] _inst_2_regi;
wire _inst_1_din;
reg [7:0] _inst_1_pout;
reg [7:0] _inst_1_regi;
wire _inst_0_din;
reg [7:0] _inst_0_pout;
reg [7:0] _inst_0_regi;

If I didn't put the signals in lists, but instead had separate variables  
for each signal, e.g. out1, out2, out3 and din1, din2, din3, the module  
will become different:

def  
make_many_sregs(clk,din1,din2,din3,WIDTH,out1,out2,out3,reset,enable,NR_REGS):
     inst=[]
     inst.append(shiftreg(clk,din1,WIDTH,out1,reset,enable))
     inst.append(shiftreg(clk,din2,WIDTH,out2,reset,enable))
     inst.append(shiftreg(clk,din3,WIDTH,out3,reset,enable))
     return inst

def convert_shiftregister_to_verilog():
     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
     WIDTH=8
     NR_REGS=3
     out1,out2,out3=[Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
     din1,din2,din3 = [Signal(bool(0)) for i in range(NR_REGS)]

     toVerilog.name="shiftregister"
     toVerilog(make_many_sregs,clk,din1,din2,din3,WIDTH,out1,out2,out3,reset,enable,NR_REGS)


Now the Verilog module has more input/output parameters:

module shiftregister (
     clk,
     din1,
     din2,
     din3,
     out1,
     out2,
     out3,
     reset,
     enable
);

input clk;
input din1;
input din2;
input din3;
output [7:0] out1;
reg [7:0] out1;
output [7:0] out2;
reg [7:0] out2;
output [7:0] out3;
reg [7:0] out3;
input reset;
input enable;


I also get complaints that Signals are either not driven or used when  
keeping signals in a list.

Since in both cases, the design that is converted will be of a specified  
size (number of shift-registers) how are they different?

I'm sorry if this an absurd question.


Thanks,
Jens Petter Abrahamsen

[myhdl-list] Re: List of Signals as input/output in a toVerilog()

[Guenter D. <dan...@we...>]

Jens Petter Abrahamsen wrote:
> Hi.
> 
> I've been experimenting much with MyHDL, I like it, and I'd like to make
> some synthesizeable code real soon. I don't have any Verilog/VHDL
> experience, maybe my questions are very basic.
> 
> All the examples I've seen of MyHDL->Verilog has a set number of
> input/output signals. I'd like to create a program which has all the
> signals inside a list (to be more flexible).
> 
> Consider the following example:
> 
> def make_many_sregs(clk,din,WIDTH,out,reset,enable,NR_REGS):
>     inst = [shiftreg(clk,din[i],WIDTH,out[i],reset,enable) for i in
> range(NR_REGS)]
>     return inst
> 
> def convert_shiftregister_to_verilog():
>     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
>     WIDTH=8
>     NR_REGS=2
>     out = [Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
>     din = [Signal(bool(0)) for i in range(NR_REGS)]
> 
As an example din is:

din = [Signal(False), Signal(False), Signal(False), Signal(False)]

... a list of signals.

There is a restriction to what type of signals can be converted with
toVerilog:

http://www.jandecaluwe.com/Tools/MyHDL/manual/conv-subset-types.html


Cheers,

Guenter

[myhdl-list] Re: List of Signals as input/output in a toVerilog()

[Jan D. <ja...@ja...>]

Guenter Dannoritzer wrote:

> There is a restriction to what type of signals can be converted with
> toVerilog:
> 
> http://www.jandecaluwe.com/Tools/MyHDL/manual/conv-subset-types.html

This describes the restriction for code inside generator functions.
I guess I'll have to add a specific section about the (more severe)
restrictions for the top-level interface of a module. In fact,
only Signals with intbv, bool or enum base types can be
converted.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: List of Signals as input/output in a toVerilog()

[Jan D. <ja...@ja...>]

Jens Petter Abrahamsen wrote:
> Hi.
> 
> I've been experimenting much with MyHDL, I like it, and I'd like to 
> make  some synthesizeable code real soon. I don't have any Verilog/VHDL  
> experience, maybe my questions are very basic.
> 
> All the examples I've seen of MyHDL->Verilog has a set number of  
> input/output signals. I'd like to create a program which has all the  
> signals inside a list (to be more flexible).
> 
> Consider the following example:
> 
> def make_many_sregs(clk,din,WIDTH,out,reset,enable,NR_REGS):
>     inst = [shiftreg(clk,din[i],WIDTH,out[i],reset,enable) for i in  
> range(NR_REGS)]
>     return inst
> 
> def convert_shiftregister_to_verilog():
>     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
>     WIDTH=8
>     NR_REGS=2
>     out = [Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
>     din = [Signal(bool(0)) for i in range(NR_REGS)]
> 
>     toVerilog.name="shiftregister"
>     toVerilog(make_many_sregs,clk,din,WIDTH,out,reset,enable,NR_REGS)
> 
> The intention is that NR_REGS gives how many shift-registers I'd like. 
> I  make the same number of data in and parallel out Signals as  
> shift-registers.
> This is the generated Verilog code. Where are din/out signals?

They are not there, basically because there is no straightforward way
to map list of signals in an interface to a Verilog object. Verilog
memories cannot be used in an interface. (I'm not considering
SystemVerilog for the time being.)

> I also get complaints that Signals are either not driven or used when  
> keeping signals in a list.

That is a symptom of the above. The signal drivers are not "found"
because lists in interfaces are not considered. Not that this
only affects the top-level interface, because the other ones
are flattened out by the convertor.

This case violates the idea that if toVerilog() succeeds without errors,
then a MyHDL simulation and the converted Verilog simulation should
do the same. So there should be errors and no output instead of
warnings.

However, I cannot just turn the warnings into errors - in other
case people want this behavior (and the simulations will match).
Also, I don't want to do strict typechecking on the MyHDL interface,
in order to allow powerful parametrization. (toVerilog() works on
a particular instance and doesn't need the parameters.) So I'll
have to think about this further.

So, at the top-level you'll have to use individual signals at
this moment. However, once you have done that you can still
proceed with lists as follows:

def top(din1, din2, ..., dinn, dout1, dout2, ...doutn, ...):
    din = [din1, din2, ..., dinn] # cut and paste from interface
    dout = [dout1, dout2, ..., doutn]

    # now use list syntax here
    ...

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com