Thread: [myhdl-list] functional verification
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From: Jacob R. <jac...@gm...> - 2007-09-24 23:15:20
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Hello all, I ran across myhdl when I first started learning Python and it looked really interesting. I am currently looking at how to do functional verification on our designs. We are a mixed signal group and we deal with analog signals at ports. Many of the HVL tools available assume only digital signals so I am expanding my search beyond specman. I like myhdl because it is Python based and I can see an easy path from design verification based on simulation to chip verification based on lab tests all within the same Python environment. I started looking at the Ruby tool, Ruby-vpi. On the surface, it looks like it can do everything I want to do but I have not dived down into the details. Also, I don't want to learn a new language. So, I have a few questions: 1. Our main simulator is ncsim. From the little I have read, I would have to write a C-program to allow myhdl to talk via PLI to ncsim. Has this already been written? What about other commercial simulators? 2. Is there any limitation in myhdl (or PLI) that would prevent analog (wreal or electrical) signals from traveling in and out of ports? 3. Has anyone built a complete verification environment in myhdl? 4. How active is the development on myhdl? The main Google links give the impression there isn't much going on. I didn't discover the posts on the newsgroups or the new site until I started digging deeper. I am glad I saw recent posts. At first I thought the project had been stagnant since version 0.5.1. jr -- Jacob Rael jac...@gm... |
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From: Jan D. <ja...@ja...> - 2007-09-25 16:08:52
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Jacob Rael wrote: > Hello all, > > I ran across myhdl when I first started learning Python and it looked > really interesting. > > I am currently looking at how to do functional verification on our > designs. We are a mixed signal group and we deal with analog signals > at ports. Many of the HVL tools available assume only digital signals > so I am expanding my search beyond specman. Currently it's the same for MyHDL. > I like myhdl because it is Python based and I can see an easy path > from design verification based on simulation to chip verification > based on lab tests all within the same Python environment. > > I started looking at the Ruby tool, Ruby-vpi. On the surface, it looks > like it can do everything I want to do but I have not dived down into > the details. Also, I don't want to learn a new language. Does Ruby-vpi support analog signals then? > So, I have a few questions: > > 1. Our main simulator is ncsim. From the little I have read, I would > have to write a C-program to allow myhdl to talk via PLI to ncsim. Has > this already been written? What about other commercial simulators? There is support out-of-the box for Icarus and cver. Look in the cosimulation dir in the distro and in the manual. As PLI is supposed to be a standard, these C modules should work with other simulators - in practice adaptations may be necessary. I know people have used this with commercial simulators in the past (also with ncsim I believe). > 2. Is there any limitation in myhdl (or PLI) that would prevent analog > (wreal or electrical) signals from traveling in and out of ports? It's not supported in the MyHDL cosimulation modules currently. I assume there's no restriction in PLI but I haven't considered this. > 4. How active is the development on myhdl? The main Google links give > the impression there isn't much going on. I didn't discover the posts > on the newsgroups or the new site until I started digging deeper. I am > glad I saw recent posts. At first I thought the project had been > stagnant since version 0.5.1. As for as I'm concerned, thinking goes on continuously but development occurs in bursts, driven by time availability and external interest. On sourceforge, I only release "official" releases, but on the MyHDL website, development snaphots can be found. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |
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From: Jacob R. <jac...@gm...> - 2007-09-25 17:44:44
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Jan, Thanks for your quick reply. I understand that open source projects tend to be a labor of love. It is encouraging that there is activity on the message boards and that you have beta releases coming out. Regarding Ruby-vpi: I have not tried it but from the documentation I have read, it appears the signals do not support analog/real ports. The too have an example of writing tests before you write any code. One thing I like about their tool is they generate template files for all aspects of the behavior verification: test runner bench design prototype spec I am becoming a big fan of templates. It is much easier to get new people ramped up and to take over tasks veterans are bored with. It is a little thing that makes ramp up time easy. Regarding cosimulation: I spent some time looking at the code differences between the two simulators and I was amazed how similar the code was. I didn't understand the differences but I assume with some time, I should be able to do a cosimulation. I also found posts on the mailing list hinting at success with ncsim. Finally, the latest version of specman seems to support analog ports. I am going to look at that to see if it will work. jr On 9/25/07, Jan Decaluwe <ja...@ja...> wrote: > Jacob Rael wrote: > > Hello all, > > > > I ran across myhdl when I first started learning Python and it looked > > really interesting. > > > > I am currently looking at how to do functional verification on our > > designs. We are a mixed signal group and we deal with analog signals > > at ports. Many of the HVL tools available assume only digital signals > > so I am expanding my search beyond specman. > > Currently it's the same for MyHDL. > > > I like myhdl because it is Python based and I can see an easy path > > from design verification based on simulation to chip verification > > based on lab tests all within the same Python environment. > > > > I started looking at the Ruby tool, Ruby-vpi. On the surface, it looks > > like it can do everything I want to do but I have not dived down into > > the details. Also, I don't want to learn a new language. > > Does Ruby-vpi support analog signals then? > > > So, I have a few questions: > > > > 1. Our main simulator is ncsim. From the little I have read, I would > > have to write a C-program to allow myhdl to talk via PLI to ncsim. Has > > this already been written? What about other commercial simulators? > > There is support out-of-the box for Icarus and cver. Look in the cosimulation > dir in the distro and in the manual. As PLI is supposed to be a standard, > these C modules should work with other simulators - in practice adaptations > may be necessary. > > I know people have used this with commercial simulators in the past > (also with ncsim I believe). > > > 2. Is there any limitation in myhdl (or PLI) that would prevent analog > > (wreal or electrical) signals from traveling in and out of ports? > > It's not supported in the MyHDL cosimulation modules currently. > I assume there's no restriction in PLI but I haven't considered this. > > > 4. How active is the development on myhdl? The main Google links give > > the impression there isn't much going on. I didn't discover the posts > > on the newsgroups or the new site until I started digging deeper. I am > > glad I saw recent posts. At first I thought the project had been > > stagnant since version 0.5.1. > > As for as I'm concerned, thinking goes on continuously but development > occurs in bursts, driven by time availability and external interest. > > On sourceforge, I only release "official" releases, but on the MyHDL > website, development snaphots can be found. > > Jan > > -- > Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com > Kaboutermansstraat 97, B-3000 Leuven, Belgium > From Python to silicon: > http://myhdl.jandecaluwe.com > > > ------------------------------------------------------------------------- > This SF.net email is sponsored by: Microsoft > Defy all challenges. Microsoft(R) Visual Studio 2005. > http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > -- Jacob Rael jac...@gm... |
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From: Jan D. <ja...@ja...> - 2007-09-26 09:53:12
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Jacob Rael wrote: > Jan, > > Thanks for your quick reply. I understand that open source projects > tend to be a labor of love. I have nothing against love (I became a father again recently which partially explains my MyHDL "inactivity") and in fact I believe any undertaking should have its dose of it, but if it stays to that in this project, I will consider it a failure :-) I am explicitly looking for industrial relevance. Actually I know that several corporations are using MyHDL, also large ones, though so far only one has "outed" itself to my knowledge (Dillon engineering). I hope others follow their example! Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |
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From: Jacob R. <jac...@gm...> - 2007-09-26 14:33:11
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I come from an RF / analog background so I typically don't write verilog that will be synthesized. I have started writing verilog models of our RF and analog blocks to help the digital guys verify connections to our blocks. The hard part there is the functional verification. Since I want lots of flexibilty, MyHDL looked very promising as a HVL. It seems to me if you are a small digital company and can't afford tools like SpecMan, it is a good choice. jr On 9/26/07, Jan Decaluwe <ja...@ja...> wrote: > Jacob Rael wrote: > > Jan, > > > > Thanks for your quick reply. I understand that open source projects > > tend to be a labor of love. > > I have nothing against love (I became a father again recently > which partially explains my MyHDL "inactivity") and in fact I > believe any undertaking should have its dose of it, but if > it stays to that in this project, I will consider it a failure :-) > > I am explicitly looking for industrial relevance. Actually > I know that several corporations are using MyHDL, also large ones, > though so far only one has "outed" itself to my knowledge > (Dillon engineering). I hope others follow their example! > > Jan > > -- > Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com > Kaboutermansstraat 97, B-3000 Leuven, Belgium > From Python to silicon: > http://myhdl.jandecaluwe.com > > > ------------------------------------------------------------------------- > This SF.net email is sponsored by: Microsoft > Defy all challenges. Microsoft(R) Visual Studio 2005. > http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > -- Jacob Rael jac...@gm... |
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From: Tom D. <TD...@di...> - 2007-09-26 16:00:09
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Jan, I have to respond to both points, almost missed your comments: > I have nothing against love (I became a father again recently > which partially explains my MyHDL "inactivity") and in fact I > believe any undertaking should have its dose of it, but if > it stays to that in this project, I will consider it a failure :-) Congratulations! My youngest of 4 is now 1 1/2 years. Which means I have not had as much time as I would like to advance our use of MyHDL in our normal project flows. Getting there now though. BTW, I also have a 5th child for this school year, a 18 year old exchange student from Belgium. She if from a little town near Chimay, not sure how close that is to you... > > I am explicitly looking for industrial relevance. Actually > I know that several corporations are using MyHDL, also large ones, > though so far only one has "outed" itself to my knowledge > (Dillon engineering). I hope others follow their example! Speaking of "outing", last week I gave a presentation at HPEC 2007 based on how we use Python to accelerate our FPGA/ASIC development. Of course mentioned MyHDL and got the chance to explain our use of it. Also pointed quite a few to the MyHDL web site. I will post the presentation and send a link to this list in the next few days. Tom |
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From: Jan D. <ja...@ja...> - 2007-10-02 14:29:53
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Tom Dillon wrote: > Jan, > Congratulations! My youngest of 4 is now 1 1/2 years. Thank you! For us it is the third child, we already had a girl (4) and a boy (7). > BTW, I also have a 5th child for this school year, a 18 year old exchange > student from Belgium. She if from a little town near Chimay, not sure how > close that is to you... Within Belgium everything is close of course, but that is in the "other" (french-speaking) part of the country. When she returns we might actually be from different countries :-) (joke for Belgians - I guess nobody in the rest of the world is interested in our internal politics.) > Speaking of "outing", last week I gave a presentation at HPEC 2007 based on > how we use Python to accelerate our FPGA/ASIC development. Of course > mentioned MyHDL and got the chance to explain our use of it. Yes, I saw that paper showing in up in google searches recently. Thanks a lot. Personally I'm getting very close to an industrial project as a consultant where I'll be allowed to use MyHDL for the first time. That would be nice personal milestone also. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |
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