myhdl-list

[myhdl-list] myHDL success: synthesized a UAR(T)

[George P. <ge...@ga...>]

Jan,

     The combination of python, myHDL, and GTKWave is powerful. With 
these tools, I succeeded in synthesizing a UART, and late last night I 
watched with joy as the LED's on my FPGA board lit up to represent the 
value of the bytes sent (at 57600 baud) from my PC!

      I used the Verilog UART design on fpga4fun.com as a reference, and 
some posts from comp.arch.fpga, and sci.electronics.design for further 
guidance. With this knowledge, I recreated the asynchronous receiver in 
myHDL. It took some time and effort, because I wanted to do things right 
and understand the concepts involved, not just blindly port code. A 
significant thing that ate up time was the almost impossible to 
understand error messages when something was wrong in the code. Is that 
something you could improve?

I learned a great deal, and am more comfortable with myHDL and hardware 
design than ever now. Now to tackle the transmit side of the UART! Keep 
up the great work on myHDL. It is clearly a success.

George

[myhdl-list] Re: myHDL success: synthesized a UAR(T)

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

>      I used the Verilog UART design on fpga4fun.com as a reference, and 
> some posts from comp.arch.fpga, and sci.electronics.design for further 
> guidance. With this knowledge, I recreated the asynchronous receiver in 
> myHDL. It took some time and effort, because I wanted to do things right 
> and understand the concepts involved, not just blindly port code. A 
> significant thing that ate up time was the almost impossible to 
> understand error messages when something was wrong in the code. Is that 
> something you could improve?

Probably, but only if you let me know the full details. The goal is that
the error messages should be crystal-clear, and currently I think
they are :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] Asynchronous receiver strange problem

[George P. <ge...@ga...>]

Hi all,

I'm having a strange problem testing my UART in-silico. I don't believe i=
t
is related to my overall design or myHDL. I'm hoping maybe someone has
come across this before.

I have verified (in simulation, as well as in hardware using LEDs and my
o-scope) that my Receiver goes through all the state transitions for an
incoming serial stream. It even appears to be shifting the correct data
into the Shift Register.

My Asynchronous Receiver module has an 8-bit debug_out port that I connec=
t
to 8 LED's on my Digilent Spartan3 FPGA dev board. A DebugProcess
continually outputs any internal signals I choose to observe.

When I try to display all eight bits of the shift register using the
debug_out port, no LED's light up on my board. But if I display four of
the Shift Register bits and four of the state bits, then the LED's light
up just fine!

In fact, I can even dislay seven of the eight bits correctly, as long as
the other bit is displaying state (All LED's stay off if I make the
remaining bit a constant 0). I can reliably reproduce this effect. What i=
n
the world is going on here?

I'm using the Digilent Spartan3 FPGA dev board, with Xilinx ISE 7.1i on
Windows XP, with myHDL 0.5dev4.

Changing the drive strength of the FPGA's LED output pins from 12ma to
24ma did not help.

----------------------------------------
Excerpt from my Receiver design:
(indentation is not necessarily correct)
----------------------------------------

state =3D Signal(intbv(0)[4:])
shift_reg =3D Signal(intbv(0)[8:])

@always(clk.posedge)
def DebugProcess():

# This fails to light up any LED's on my dev board
#    debug_out.next[0] =3D shift_reg[0]
#    debug_out.next[1] =3D shift_reg[1]
#    debug_out.next[2] =3D shift_reg[2]
#    debug_out.next[3] =3D shift_reg[3]

#    debug_out.next[4] =3D shift_reg[4]
#    debug_out.next[5] =3D shift_reg[5]
#    debug_out.next[6] =3D shift_reg[6]
#    debug_out.next[7] =3D shift_reg[7]

# This lights up the LED's ok!
#    debug_out.next[0] =3D shift_reg[0]
#    debug_out.next[1] =3D shift_reg[1]
#    debug_out.next[2] =3D shift_reg[2]
#    debug_out.next[3] =3D state[3] # NOTE: state here makes it work

#    debug_out.next[4] =3D shift_reg[0]
#    debug_out.next[5] =3D shift_reg[1]
#    debug_out.next[6] =3D shift_reg[2]
#    debug_out.next[7] =3D shift_reg[3]


# This lights up the LED's ok also!
    debug_out.next[0] =3D state[0]
    debug_out.next[1] =3D state[1]
    debug_out.next[2] =3D state[2]
    debug_out.next[3] =3D state[3]

    debug_out.next[4] =3D shift_reg[0]
    debug_out.next[5] =3D shift_reg[1]
    debug_out.next[6] =3D shift_reg[2]
    debug_out.next[7] =3D shift_reg[3]


--------------------------------------------

Thanks,

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Asynchronous receiver strange problem

[Haitao Z. <ha...@gm...>]

You didn't give much detail on what LEDs are lighting up and what are
not, but anyway this is not a list to debug designs. One thing you
want to consider is how fast you are clocking the shift registers.
Your eyes and the LEDs can't respond to the normal clock rate used in
the digital design. You can only see relatively static signals.

Haitao

On 11/23/05, George Pantazopoulos <ge...@ga...> wrote:
>
> Hi all,
>
> I'm having a strange problem testing my UART in-silico. I don't believe i=
t
> is related to my overall design or myHDL. I'm hoping maybe someone has
> come across this before.
>
> I have verified (in simulation, as well as in hardware using LEDs and my
> o-scope) that my Receiver goes through all the state transitions for an
> incoming serial stream. It even appears to be shifting the correct data
> into the Shift Register.
>
> My Asynchronous Receiver module has an 8-bit debug_out port that I connec=
t
> to 8 LED's on my Digilent Spartan3 FPGA dev board. A DebugProcess
> continually outputs any internal signals I choose to observe.
>
> When I try to display all eight bits of the shift register using the
> debug_out port, no LED's light up on my board. But if I display four of
> the Shift Register bits and four of the state bits, then the LED's light
> up just fine!
>
> In fact, I can even dislay seven of the eight bits correctly, as long as
> the other bit is displaying state (All LED's stay off if I make the
> remaining bit a constant 0). I can reliably reproduce this effect. What i=
n
> the world is going on here?
>
> I'm using the Digilent Spartan3 FPGA dev board, with Xilinx ISE 7.1i on
> Windows XP, with myHDL 0.5dev4.
>
> Changing the drive strength of the FPGA's LED output pins from 12ma to
> 24ma did not help.
>
> ----------------------------------------
> Excerpt from my Receiver design:
> (indentation is not necessarily correct)
> ----------------------------------------
>
> state =3D Signal(intbv(0)[4:])
> shift_reg =3D Signal(intbv(0)[8:])
>
> @always(clk.posedge)
> def DebugProcess():
>
> # This fails to light up any LED's on my dev board
> #    debug_out.next[0] =3D shift_reg[0]
> #    debug_out.next[1] =3D shift_reg[1]
> #    debug_out.next[2] =3D shift_reg[2]
> #    debug_out.next[3] =3D shift_reg[3]
>
> #    debug_out.next[4] =3D shift_reg[4]
> #    debug_out.next[5] =3D shift_reg[5]
> #    debug_out.next[6] =3D shift_reg[6]
> #    debug_out.next[7] =3D shift_reg[7]
>
> # This lights up the LED's ok!
> #    debug_out.next[0] =3D shift_reg[0]
> #    debug_out.next[1] =3D shift_reg[1]
> #    debug_out.next[2] =3D shift_reg[2]
> #    debug_out.next[3] =3D state[3] # NOTE: state here makes it work
>
> #    debug_out.next[4] =3D shift_reg[0]
> #    debug_out.next[5] =3D shift_reg[1]
> #    debug_out.next[6] =3D shift_reg[2]
> #    debug_out.next[7] =3D shift_reg[3]
>
>
> # This lights up the LED's ok also!
>     debug_out.next[0] =3D state[0]
>     debug_out.next[1] =3D state[1]
>     debug_out.next[2] =3D state[2]
>     debug_out.next[3] =3D state[3]
>
>     debug_out.next[4] =3D shift_reg[0]
>     debug_out.next[5] =3D shift_reg[1]
>     debug_out.next[6] =3D shift_reg[2]
>     debug_out.next[7] =3D shift_reg[3]
>
>
> --------------------------------------------
>
> Thanks,
>
> --
> George Pantazopoulos
> http://www.gammaburst.net
>
>
>
> -------------------------------------------------------
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[myhdl-list] Re: Asynchronous receiver strange problem

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi all,
> 
> I'm having a strange problem testing my UART in-silico. I don't believe it
> is related to my overall design or myHDL. I'm hoping maybe someone has
> come across this before.
> 

I suggest to seek help on comp.lang.fpga for issues such as this. It's
quite active and I think you have a good chance of getting help.

Of course, you'll have to illustrate the issue using the generated
Verilog, at least for the time being :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com