Haitao Zhang wrote:
> This may be common knowledge but I may as well post it in case someone
> else run into similiar problem:
>
> toVerilog tries to find the instance name of what it is assigned to,
> i.e. the lname in the following expression:
> lname = toVerilog(...)
> It does this by inspecting the source file. When run interactively
> some of the functions it calls fails because it can't get the info
> from stdin. When running from a file (either a standalone script or
> through execfile) it works fine.
>
> Haitao
Exactly right!
This issue had been reported before, but in a private e-mail
exchange. (Thanks for using the newsgroup to report issues -
I encourage everyone to do the same.)
The error message currently comes from the inspect method -
MyHDL doesn't check anything so this this could be improved.
Patches welcome!
Regards, Jan
--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Using Python as a hardware description language:
http://jandecaluwe.com/Tools/MyHDL/Overview.html
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