Thread: [myhdl-list] parallel to serial
Brought to you by:
jandecaluwe
Menu
▾
▴
myhdl-list
|
From: Edward V. <dev...@sb...> - 2016-01-15 02:27:48
|
Hello All,I found this VHDL code on the web.library ieee;
use ieee.std_logic_1164.all;
entity piso is
port(
clk,load : in std_logic;
pi : in std_logic_vector(35 downto 0);
so : out std_logic);
end piso;
architecture arch of piso is
signal t : std_logic;
signal temp: std_logic_vector(35 downto 0);
begin
process (clk,pi,load)
begin
if (load='1') then
temp(35 downto 0) <= pi(35 downto 0);
elsif (CLK'event and CLK='1') then
t <= temp(35);
temp(35 downto 1) <= temp(34 downto 0);
temp(0) <= '0';
end if;
end process;
so <= t;
end arch;I create a test bench in ise and it appears to be okay.from myhdl import *
import argparse
W0 = 36
pp0 = Signal(intbv(0)[W0:])
ss0 = Signal(bool(0))
clk = Signal(bool(0))
ld = Signal(bool(0))
def cliparse():
parser = argparse.ArgumentParser()
parser.add_argument("--build", default=False, action='store_true')
parser.add_argument("--test", default=False, action='store_true')
parser.add_argument("--convert", default=False, action='store_true')
args = parser.parse_args()
return args
def para2ser(clk, pp0, ss0, ld):
t = Signal(bool(0))
temp = Signal(intbv(0)[W0:])
@always(clk.posedge)
def logic():
if (ld == 1):
temp[36:0].next = pp0[36:0]
else:
t.next = int(temp[36:35])
temp[36:1].next = temp[35:0]
temp[1:].next = int(0)
ss0.next = t
return logic
def tb(clk, pp0, ss0, ld):
instance_1 = para2ser(clk, pp0, ss0, ld)
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
pp0.next = 34359738368
yield clk.posedge
ld.next = 1
yield clk.posedge
ld.next = 0
yield clk.posedge
print ("%s %d") % (bin(pp0,36), ss0 )
for i in range(36):
yield clk.posedge
print ("%d %s %d") % (i, bin(pp0,36), ss0 )
raise StopSimulation
return instances()
def convert(args):
toVHDL(para2ser,clk, pp0, ss0, ld)
toVerilog(para2ser,clk, pp0, ss0, ld)
def main():
args = cliparse()
if args.test:
tb_fsm = traceSignals(tb,clk, pp0, ss0, ld)
sim = Simulation(tb_fsm)
sim.run()
if args.convert:
convert(args)
if __name__ == '__main__':
main()
Can someone tell me what I am doing wrong? I think it this line
temp[1:].next = int(0)I have tried without the int and I get the same results when I run python para2ser.py --test
Thanks
Regards, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 |
|
From: Christopher F. <chr...@gm...> - 2016-01-15 02:58:18
|
Edward,
When assign intbv bit slices you need to:
temp.next[1:0] = 0
Hope that helps,
Chris
On 1/14/16 8:26 PM, Edward Vidal wrote:
> Hello All,
> I found this VHDL code on the web.
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity piso is
> port(
> clk,load : in std_logic;
> pi : in std_logic_vector(35 downto 0);
> so : out std_logic);
> end piso;
>
> architecture arch of piso is
>
> signal t : std_logic;
> signal temp: std_logic_vector(35 downto 0);
>
> begin
>
> process (clk,pi,load)
> begin
> if (load='1') then
> temp(35 downto 0) <= pi(35 downto 0);
> elsif (CLK'event and CLK='1') then
> t <= temp(35);
> temp(35 downto 1) <= temp(34 downto 0);
> temp(0) <= '0';
> end if;
> end process;
>
> so <= t;
>
> end arch;
> I create a test bench in ise and it appears to be okay.
> from myhdl import *
> import argparse
> W0 = 36
> pp0 = Signal(intbv(0)[W0:])
> ss0 = Signal(bool(0))
> clk = Signal(bool(0))
> ld = Signal(bool(0))
> def cliparse():
> parser = argparse.ArgumentParser()
> parser.add_argument("--build", default=False, action='store_true')
> parser.add_argument("--test", default=False, action='store_true')
> parser.add_argument("--convert", default=False, action='store_true')
> args = parser.parse_args()
> return args
>
> def para2ser(clk, pp0, ss0, ld):
>
> t = Signal(bool(0))
> temp = Signal(intbv(0)[W0:])
> @always(clk.posedge)
> def logic():
>
> if (ld == 1):
> temp[36:0].next = pp0[36:0]
> else:
> t.next = int(temp[36:35])
>
> temp[36:1].next = temp[35:0]
> temp[1:].next = int(0)
> ss0.next = t
>
> return logic
>
> def tb(clk, pp0, ss0, ld):
> instance_1 = para2ser(clk, pp0, ss0, ld)
>
> @always(delay(10))
> def clkgen():
> clk.next = not clk
> @instance
> def stimulus():
>
> pp0.next = 34359738368
> yield clk.posedge
> ld.next = 1
> yield clk.posedge
> ld.next = 0
> yield clk.posedge
> print ("%s %d") % (bin(pp0,36), ss0 )
> for i in range(36):
> yield clk.posedge
> print ("%d %s %d") % (i, bin(pp0,36), ss0 )
> raise StopSimulation
>
> return instances()
> def convert(args):
> toVHDL(para2ser,clk, pp0, ss0, ld)
> toVerilog(para2ser,clk, pp0, ss0, ld)
>
>
> def main():
> args = cliparse()
> if args.test:
> tb_fsm = traceSignals(tb,clk, pp0, ss0, ld)
> sim = Simulation(tb_fsm)
> sim.run()
> if args.convert:
> convert(args)
>
> if __name__ == '__main__':
> main()
> Can someone tell me what I am doing wrong?
> I think it this line
> temp[1:].next = int(0)
> I have tried without the int and I get the same results when I run
> python para2ser.py --test
> Thanks
> Regards,
> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
|
|
From: Jan D. <ja...@ja...> - 2016-01-15 08:16:40
|
Also, why not assign single bits to indices
instead of slices, like in the VHDL?
On 15/01/16 03:58, Christopher Felton wrote:
> Edward,
>
> When assign intbv bit slices you need to:
>
> temp.next[1:0] = 0
>
> Hope that helps,
> Chris
>
> On 1/14/16 8:26 PM, Edward Vidal wrote:
>> Hello All,
>> I found this VHDL code on the web.
>> library ieee;
>> use ieee.std_logic_1164.all;
>>
>> entity piso is
>> port(
>> clk,load : in std_logic;
>> pi : in std_logic_vector(35 downto 0);
>> so : out std_logic);
>> end piso;
>>
>> architecture arch of piso is
>>
>> signal t : std_logic;
>> signal temp: std_logic_vector(35 downto 0);
>>
>> begin
>>
>> process (clk,pi,load)
>> begin
>> if (load='1') then
>> temp(35 downto 0) <= pi(35 downto 0);
>> elsif (CLK'event and CLK='1') then
>> t <= temp(35);
>> temp(35 downto 1) <= temp(34 downto 0);
>> temp(0) <= '0';
>> end if;
>> end process;
>>
>> so <= t;
>>
>> end arch;
>> I create a test bench in ise and it appears to be okay.
>> from myhdl import *
>> import argparse
>> W0 = 36
>> pp0 = Signal(intbv(0)[W0:])
>> ss0 = Signal(bool(0))
>> clk = Signal(bool(0))
>> ld = Signal(bool(0))
>> def cliparse():
>> parser = argparse.ArgumentParser()
>> parser.add_argument("--build", default=False, action='store_true')
>> parser.add_argument("--test", default=False, action='store_true')
>> parser.add_argument("--convert", default=False, action='store_true')
>> args = parser.parse_args()
>> return args
>>
>> def para2ser(clk, pp0, ss0, ld):
>>
>> t = Signal(bool(0))
>> temp = Signal(intbv(0)[W0:])
>> @always(clk.posedge)
>> def logic():
>>
>> if (ld == 1):
>> temp[36:0].next = pp0[36:0]
>> else:
>> t.next = int(temp[36:35])
>>
>> temp[36:1].next = temp[35:0]
>> temp[1:].next = int(0)
>> ss0.next = t
>>
>> return logic
>>
>> def tb(clk, pp0, ss0, ld):
>> instance_1 = para2ser(clk, pp0, ss0, ld)
>>
>> @always(delay(10))
>> def clkgen():
>> clk.next = not clk
>> @instance
>> def stimulus():
>>
>> pp0.next = 34359738368
>> yield clk.posedge
>> ld.next = 1
>> yield clk.posedge
>> ld.next = 0
>> yield clk.posedge
>> print ("%s %d") % (bin(pp0,36), ss0 )
>> for i in range(36):
>> yield clk.posedge
>> print ("%d %s %d") % (i, bin(pp0,36), ss0 )
>> raise StopSimulation
>>
>> return instances()
>> def convert(args):
>> toVHDL(para2ser,clk, pp0, ss0, ld)
>> toVerilog(para2ser,clk, pp0, ss0, ld)
>>
>>
>> def main():
>> args = cliparse()
>> if args.test:
>> tb_fsm = traceSignals(tb,clk, pp0, ss0, ld)
>> sim = Simulation(tb_fsm)
>> sim.run()
>> if args.convert:
>> convert(args)
>>
>> if __name__ == '__main__':
>> main()
>> Can someone tell me what I am doing wrong?
>> I think it this line
>> temp[1:].next = int(0)
>> I have tried without the int and I get the same results when I run
>> python para2ser.py --test
>> Thanks
>> Regards,
>> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>>
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>>
>>
>>
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
World-class digital design: http://www.easics.com
|
|
From: Edward V. <dev...@sb...> - 2016-01-15 17:46:21
|
Hello All,I can not believe that 3 lines are such a problem.This t.next = (temp[36:35]) generates t <= temp(36-1 downto 35)(0);which does not appear correct. This is what I t <= temp(35); This t.next = int(temp[36:35]) generates t <= stdl(to_integer(temp(36-1 downto 35)));which I believe might be okay. This temp[36:1].next = temp[35:0] generates temp(36-1 downto 1) <= temp(35-1 downto 0);which be taking the lower 34 bits to upper 34 of temp. I am using @always(clk.posedge) could this be the problem? https://gist.github.com/develone/77732a2a1ab452e5f1f8 python gistfile1.txt --test does not perform the desired results.python gistfile1.txt --convert generates the Verilog & VHDL files Thanks for all the help. Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Friday, January 15, 2016 1:16 AM, Jan Decaluwe <ja...@ja...> wrote: Also, why not assign single bits to indices instead of slices, like in the VHDL? On 15/01/16 03:58, Christopher Felton wrote: > Edward, > > When assign intbv bit slices you need to: > > temp.next[1:0] = 0 > > Hope that helps, > Chris > > On 1/14/16 8:26 PM, Edward Vidal wrote: >> Hello All, >> I found this VHDL code on the web. >> library ieee; >> use ieee.std_logic_1164.all; >> >> entity piso is >> port( >> clk,load : in std_logic; >> pi : in std_logic_vector(35 downto 0); >> so : out std_logic); >> end piso; >> >> architecture arch of piso is >> >> signal t : std_logic; >> signal temp: std_logic_vector(35 downto 0); >> >> begin >> >> process (clk,pi,load) >> begin >> if (load='1') then >> temp(35 downto 0) <= pi(35 downto 0); >> elsif (CLK'event and CLK='1') then >> t <= temp(35); >> temp(35 downto 1) <= temp(34 downto 0); >> temp(0) <= '0'; >> end if; >> end process; >> >> so <= t; >> >> end arch; >> I create a test bench in ise and it appears to be okay. >> from myhdl import * >> import argparse >> W0 = 36 >> pp0 = Signal(intbv(0)[W0:]) >> ss0 = Signal(bool(0)) >> clk = Signal(bool(0)) >> ld = Signal(bool(0)) >> def cliparse(): >> parser = argparse.ArgumentParser() >> parser.add_argument("--build", default=False, action='store_true') >> parser.add_argument("--test", default=False, action='store_true') >> parser.add_argument("--convert", default=False, action='store_true') >> args = parser.parse_args() >> return args >> >> def para2ser(clk, pp0, ss0, ld): >> >> t = Signal(bool(0)) >> temp = Signal(intbv(0)[W0:]) >> @always(clk.posedge) >> def logic(): >> >> if (ld == 1): >> temp[36:0].next = pp0[36:0] >> else: >> t.next = int(temp[36:35]) >> >> temp[36:1].next = temp[35:0] >> temp[1:].next = int(0) >> ss0.next = t >> >> return logic >> >> def tb(clk, pp0, ss0, ld): >> instance_1 = para2ser(clk, pp0, ss0, ld) >> >> @always(delay(10)) >> def clkgen(): >> clk.next = not clk >> @instance >> def stimulus(): >> >> pp0.next = 34359738368 >> yield clk.posedge >> ld.next = 1 >> yield clk.posedge >> ld.next = 0 >> yield clk.posedge >> print ("%s %d") % (bin(pp0,36), ss0 ) >> for i in range(36): >> yield clk.posedge >> print ("%d %s %d") % (i, bin(pp0,36), ss0 ) >> raise StopSimulation >> >> return instances() >> def convert(args): >> toVHDL(para2ser,clk, pp0, ss0, ld) >> toVerilog(para2ser,clk, pp0, ss0, ld) >> >> >> def main(): >> args = cliparse() >> if args.test: >> tb_fsm = traceSignals(tb,clk, pp0, ss0, ld) >> sim = Simulation(tb_fsm) >> sim.run() >> if args.convert: >> convert(args) >> >> if __name__ == '__main__': >> main() >> Can someone tell me what I am doing wrong? >> I think it this line >> temp[1:].next = int(0) >> I have tried without the int and I get the same results when I run >> python para2ser.py --test >> Thanks >> Regards, >> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 >> >> >> ------------------------------------------------------------------------------ >> Site24x7 APM Insight: Get Deep Visibility into Application Performance >> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month >> Monitor end-to-end web transactions and take corrective actions now >> Troubleshoot faster and improve end-user experience. Signup Now! >> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 >> >> >> >> _______________________________________________ >> myhdl-list mailing list >> myh...@li... >> https://lists.sourceforge.net/lists/listinfo/myhdl-list >> > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
|
From: Christopher F. <chr...@gm...> - 2016-01-15 21:23:38
|
On 1/15/2016 11:45 AM, Edward Vidal wrote: > Hello All,I can not believe that 3 lines are such a problem. I posted a short reply in the gist comments: https://gist.github.com/develone/77732a2a1ab452e5f1f8 |
|
From: Jan D. <ja...@ja...> - 2016-01-15 22:39:23
|
On 15/01/16 18:45, Edward Vidal wrote: > Hello All, > I can not believe that 3 lines are such a problem. > This t.next = (temp[36:35]) generates t <= temp(36-1 downto 35)(0); > which does not appear correct. Why not? But still, if working with single bits, why don't you simply assign an index instead of a slice? > This temp[36:1].next = temp[35:0] generates temp(36-1 downto 1) <= temp(35-1 downto 0); > which be taking the lower 34 bits to upper 34 of temp. That makes no sense in MyHDL, and will not simulate. Hence, you cannot draw any conclusions from conversion, even if it doesn't complain. Simulate first. > I am using @always(clk.posedge) could this be the problem? No. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |
|
From: Edward V. <dev...@sb...> - 2016-01-16 01:23:00
|
Hello All,What Chris provided worked okay.Jan is correct in one of tries the code converted but would not simulate.The https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/para2ser.py was added to my https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/test_top.py python test_top.py --test is a simulation python test_top.py --convert generates a Verilog file. Placing the files para2ser.py, ex_catboard_jpeg.py, jpeg.py, l2r.py, sh_reg.py, signed2twoscomplement.py, and test_top.py in my rhea/examples/build folder. This done on a Ubuntu 12.04 with Xilinx 14.6 also testing on RPi2B w/Yosys, Arachne-pnr, and ICEPack Should I be seeing more usage with around 30 plus instances?see below vidal@ws009:~/wkg/rhea/examples/build$ python ex_jpeg_xula2.py ** ToVerilogWarning: Signal is driven but not read: ss0 ** ToVerilogWarning: Signal is not driven: ld ** ToVerilogWarning: Signal is not driven: si1 ** ToVerilogWarning: Signal is not driven: si0 ** ToVerilogWarning: Signal is not driven: sig1 ** ToVerilogWarning: Signal is not driven: sig0 ** ToVerilogWarning: Signal is not driven: sig3 ** ToVerilogWarning: Signal is not driven: sig2 ** ToVerilogWarning: Signal is not driven: sig5 ** ToVerilogWarning: Signal is not driven: sig4 ** ToVerilogWarning: Signal is not driven: sig7 ** ToVerilogWarning: Signal is not driven: sig6 ** ToVerilogWarning: Signal is driven but not read: z4 ** ToVerilogWarning: Signal is driven but not read: z5 ** ToVerilogWarning: Signal is driven but not read: done5 ** ToVerilogWarning: Signal is driven but not read: done4 ** ToVerilogWarning: Signal is driven but not read: done7 ** ToVerilogWarning: Signal is driven but not read: done6 ** ToVerilogWarning: Signal is driven but not read: done1 ** ToVerilogWarning: Signal is driven but not read: done0 ** ToVerilogWarning: Signal is driven but not read: done3 ** ToVerilogWarning: Signal is driven but not read: done2 ** ToVerilogWarning: Signal is driven but not read: z6 ** ToVerilogWarning: Signal is driven but not read: z7 ** ToVerilogWarning: Signal is driven but not read: z0 ** ToVerilogWarning: Signal is driven but not read: z1 ** ToVerilogWarning: Signal is driven but not read: z2 ** ToVerilogWarning: Signal is driven but not read: z3 ** ToVerilogWarning: Signal is not driven: fB3 ** ToVerilogWarning: Signal is not driven: fB2 ** ToVerilogWarning: Signal is driven but not read: po6 ** ToVerilogWarning: Signal is driven but not read: po4 ** ToVerilogWarning: Signal is driven but not read: po2 ** ToVerilogWarning: Signal is driven but not read: po1 ** ToVerilogWarning: Signal is not driven: pp0 ** ToVerilogWarning: Signal is not driven: fB7 ** ToVerilogWarning: Signal is not driven: si6 ** ToVerilogWarning: Signal is not driven: reset ** ToVerilogWarning: Signal is not driven: si5 ** ToVerilogWarning: Signal is not driven: si4 ** ToVerilogWarning: Signal is driven but not read: po7 ** ToVerilogWarning: Signal is driven but not read: po5 ** ToVerilogWarning: Signal is driven but not read: po3 ** ToVerilogWarning: Signal is driven but not read: po0 ** ToVerilogWarning: Signal is not driven: si3 ** ToVerilogWarning: Signal is not driven: si2 ** ToVerilogWarning: Signal is not driven: fB1 ** ToVerilogWarning: Signal is not driven: fB0 ** ToVerilogWarning: Signal is not driven: si7 ** ToVerilogWarning: Signal is not driven: fB6 ** ToVerilogWarning: Signal is not driven: fB5 ** ToVerilogWarning: Signal is not driven: fB4 removing xilinx/xula2.v moving xula2.v --> xilinx/ Project name : xula2.xise Number of Slice Registers: 0 out of 11,440 0% Number of LUT Flip Flop pairs used: 0 Number of Slice Registers: 0 out of 11,440 0% Number of LUT Flip Flop pairs used: 0 {'fmax': -1, 'syn': {'dsp': (0, 2, 0), 'reg': (0, 11440, 0)}} removing xilinx/xula2.v moving xula2.v --> xilinx/ Project name : xula2.xise Number of Slice Registers: 0 out of 11,440 0% Number of LUT Flip Flop pairs used: 0 Number of Slice Registers: 0 out of 11,440 0% Number of LUT Flip Flop pairs used: 0 {'fmax': -1, 'syn': {'dsp': (0, 2, 0), 'reg': (0, 11440, 0)}} Thanks for the help. Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Friday, January 15, 2016 3:39 PM, Jan Decaluwe <ja...@ja...> wrote: On 15/01/16 18:45, Edward Vidal wrote: > Hello All, > I can not believe that 3 lines are such a problem. > This t.next = (temp[36:35]) generates t <= temp(36-1 downto 35)(0); > which does not appear correct. Why not? But still, if working with single bits, why don't you simply assign an index instead of a slice? > This temp[36:1].next = temp[35:0] generates temp(36-1 downto 1) <= temp(35-1 downto 0); > which be taking the lower 34 bits to upper 34 of temp. That makes no sense in MyHDL, and will not simulate. Hence, you cannot draw any conclusions from conversion, even if it doesn't complain. Simulate first. > I am using @always(clk.posedge) could this be the problem? No. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
×
Want the latest updates on software, tech news, and AI?
Get latest updates about software, tech news, and AI from SourceForge directly in your inbox once a month.
Thanks for helping keep SourceForge clean.
X