Thread: [myhdl-list] Bug in MyHDL compiler?

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When I try to run the following code in a file, it terminates with an
error. It appears to occur when a memory list is used in a function
that doesn't return something directly executable, even though I am
throwing away the other return value (but I'd like to be able to
return a usable function that is synthesized into a verilog
talk/function). What functions do I need to look at in the compiler to
add this feature, or why is it impossible in the current system?

Thanks,
David

from myhdl import *

def test(a, o):
	mem = [Signal(intbv(i)[32:]) for i in range(32)]

	@always_comb
	def logic():
		o.next = mem[a]

	def foo():
		pass

	return logic, foo

clk = Signal(bool(0))

@always(delay(10))
def clkgen():
	clk.next = not clk

def tb(clk):
	a = Signal(intbv(0)[32:])
	o = Signal(intbv(0)[32:])
	t_logic, foo = test(a,o)
	counter = Signal(intbv(0)[4:])

	@always(clk.posedge)
	def logic():
		counter.next = (counter + 1) % 16
		if counter == 3:
			a.next = 0
		else:
			a.next = 7

	return t_logic, logic

toVerilog(tb, clk)