Hello All,
Testing https://github.com/udara28/SDRAM_Controller.git
python Conversion generates on Raspberry Pi 2B
-rw-r--r-- 1 root root 10774 Oct 14 19:48 MySdramCntl.v
-rw-r--r-- 1 root root 12320 Oct 14 19:48 MySdramCntl.vhd
-rw-r--r-- 1 root root 4346 Oct 14 19:48 pck_myhdl_10.vhd
This works okay on several systems see below.
python test_controller.py on Raspberry Pi 2B
Traceback (most recent call last):
File "test_controller.py", line 30, in <module>
sdram_Inst = sdram(clk_i,sd_intf_Inst,show_command=False)
File "/home/root/SDRAM_Controller/sdram.py", line 51, in sdram
@always(clk.posedge)
File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py", line 59, in _always_decorator
return _Always(func, args)
File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py", line 78, in __init__
symdict.update(zip(freevars, closure))
File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py", line 77, in <genexpr>
closure = (c.cell_contents for c in func.__closure__)
ValueError: Cell is empty
python test_controller.py
vidal@vidal-MX6438:~/wkg/SDRAM_Controller$ python test_controller.py
BANK 0 STATE : [CHANGE] Uninitialized -> Initialized @ 3999
BANK 1 STATE : [CHANGE] Uninitialized -> Initialized @ 3999
BANK 2 STATE : [CHANGE] Uninitialized -> Initialized @ 3999
BANK 3 STATE : [CHANGE] Uninitialized -> Initialized @ 3999
--------------------------
Mode | CAS | Burst
--------|-------|---------
Burst | 3 | 1
--------------------------
DATA : [WRITE] Addr: 120 Data: 23
SDRAM : [READ] Commnad registered
STATE : [READ] Data Ready @ 4167 value : 23
Data Value : 23 clk : 4169
<class 'myhdl._SuspendSimulation'>: Simulated 7500 timesteps
Regards,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 |
