myhdl-list

[myhdl-list] error in verilog?

[Mr C C. <ch...@be...>]

If (probably by using MyHDL incorrectly) yosys reports a syntax error 
with generated verilog, is this a bug with MyHDL (shouldn't MyHDL be 
reporting my idiocy)

being as I have no idea what I'm doing or what the error is, I'd 
struggle to reproduce it in a minimal case, but it is just a Makefile 
and a couple of python scripts...

this verilog

         0 <= 1'b0;

is where the error is happening

but I'm doing something dumb obviously because earlier

input [7:0] LEDS;

I'm attempting (probably incorrectly) to pass a top level output to a 
module where its manipulated

although the scripts are small I've not attached them as this usually 
triggers netiquette SJW's for some reason and I just can't be bothered.....

Re: [myhdl-list] error in verilog?

[Christopher F. <chr...@gm...>]

On 2/26/16 4:36 AM, Mr C Camacho wrote:
> If (probably by using MyHDL incorrectly) yosys reports a syntax
> error with generated verilog, is this a bug with MyHDL (shouldn't
> MyHDL be reporting my idiocy)

If your testbench passes and the converted Verilog
fails then it is something worth looking at to see
if a bug exists.  Your best bet to getting working
converted V* is to test the MyHDL code.

>
> being as I have no idea what I'm doing or what the error is, I'd
> struggle to reproduce it in a minimal case, but it is just a
> Makefile and a couple of python scripts...
>
> this verilog
>
> 0 <= 1'b0;

You might have forgotten the ".next" in an assignment.

Regards,
Chris

Re: [myhdl-list] error in verilog?

[Mr C C. <ch...@be...>]

it will simulate without error, unsurprisingly the waveform doesn't look 
to be doing anything (even if I change the clock down counter) 12mhz 
being a little fast to see things changing!

but yeah if it simulates and passes through MyHDL but isn't valid 
verilog then there is a potential bug (at very least in MyHDL's error 
checking) - even if I'm using MyHDL wrong ;) !

alas I'm going to need someone's help to isolate the issue before it 
could even be reported as a bug...

On 26/02/16 13:25, Christopher Felton wrote:
> On 2/26/16 4:36 AM, Mr C Camacho wrote:
>> If (probably by using MyHDL incorrectly) yosys reports a syntax
>> error with generated verilog, is this a bug with MyHDL (shouldn't
>> MyHDL be reporting my idiocy)
> If your testbench passes and the converted Verilog
> fails then it is something worth looking at to see
> if a bug exists.  Your best bet to getting working
> converted V* is to test the MyHDL code.
>
>> being as I have no idea what I'm doing or what the error is, I'd
>> struggle to reproduce it in a minimal case, but it is just a
>> Makefile and a couple of python scripts...
>>
>> this verilog
>>
>> 0 <= 1'b0;
> You might have forgotten the ".next" in an assignment.
>
> Regards,
> Chris
>
>
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