Thread: [myhdl-list] Weird error
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From: Merkourios K. <mer...@gm...> - 2016-01-16 11:56:04
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Hallo guys, I tried to run this code: def dff(q,d,clk,rst): @always(clk.posedge,rst.posedge) def logic(): if rst==1: q.next=0 else: q.next=d return logic def param_reg(q,d,clk,rst,width=4,n=2): signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)] instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i in range(n)] @always_comb def logic(): signal_list[0].next=d q.next=signal_list[n+1] return logic,instance_list but I get the following error:AlwaysCombError: signal (signal_list) used as inout in always_comb function argument when i change the code of param_reg to : def param_reg(q,d,clk,rst,width=4,n=2): signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)] instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i in range(n)] @always_comb def logic(): signal_list[0].next=d @always_comb def logic2(): q.next=signal_list[n+1] return logic,instance_list,logic2 It works fine. Do you know whats the problem? Thanks |
From: Nicolas P. <ni...@aa...> - 2016-01-18 11:08:04
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Le 16/01/2016 12:55, Merkourios Katsimpris a écrit : > Hallo guys, > > I tried to run this code: > > def dff(q,d,clk,rst): > > @always(clk.posedge,rst.posedge) > def logic(): > if rst==1: > q.next=0 > else: > q.next=d > > return logic > > > def param_reg(q,d,clk,rst,width=4,n=2): > > signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)] > instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i > in range(n)] > > @always_comb > def logic(): > signal_list[0].next=d > q.next=signal_list[n+1] > > return logic,instance_list > > > but I get the following error:AlwaysCombError: signal (signal_list) used > as inout in always_comb function argument > > when i change the code of param_reg to : > > def param_reg(q,d,clk,rst,width=4,n=2): > > signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)] > instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i > in range(n)] > > @always_comb > def logic(): > signal_list[0].next=d > @always_comb > def logic2(): > q.next=signal_list[n+1] > > return logic,instance_list,logic2 > > It works fine. Do you know whats the problem? Looks like a bug. I reproduced it with latest version from github. However, be careful that "q.next=signal_list[n+1]" is not correct. It should be "q.next=signal_list[n]". regards, Nicolas > > Thanks > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > . > -- *Nicolas PINAULT R&D electronics engineer *** ni...@aa... <mailto:ni...@aa...> *AATON-Digital* 38000 Grenoble - France Tel +33 4 7642 9550 http://www.aaton.com http://www.transvideo.eu French Technologies for Film and Digital Cinematography Follow us on Twitter @Aaton_Digital @Transvideo_HD Like us on Facebook https://www.facebook.com/AatonDigital |
From: Merkourios K. <mer...@gm...> - 2016-01-18 11:41:04
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Hallo Nicolas, Thanks for the reply.You are right it should be "q.next=signal_list[n]". I have corrected it after I have sent the email. Best regards, Merk On 18/01/2016 01:07 μμ, Nicolas Pinault wrote: > Le 16/01/2016 12:55, Merkourios Katsimpris a écrit : >> Hallo guys, >> >> I tried to run this code: >> >> def dff(q,d,clk,rst): >> >> @always(clk.posedge,rst.posedge) >> def logic(): >> if rst==1: >> q.next=0 >> else: >> q.next=d >> >> return logic >> >> >> def param_reg(q,d,clk,rst,width=4,n=2): >> >> signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)] >> instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i >> in range(n)] >> >> @always_comb >> def logic(): >> signal_list[0].next=d >> q.next=signal_list[n+1] >> >> return logic,instance_list >> >> >> but I get the following error:AlwaysCombError: signal (signal_list) used >> as inout in always_comb function argument >> >> when i change the code of param_reg to : >> >> def param_reg(q,d,clk,rst,width=4,n=2): >> >> signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)] >> instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i >> in range(n)] >> >> @always_comb >> def logic(): >> signal_list[0].next=d >> @always_comb >> def logic2(): >> q.next=signal_list[n+1] >> >> return logic,instance_list,logic2 >> >> It works fine. Do you know whats the problem? > Looks like a bug. I reproduced it with latest version from github. > However, be careful that "q.next=signal_list[n+1]" is not correct. It > should be "q.next=signal_list[n]". > > regards, > Nicolas >> Thanks >> >> ------------------------------------------------------------------------------ >> Site24x7 APM Insight: Get Deep Visibility into Application Performance >> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month >> Monitor end-to-end web transactions and take corrective actions now >> Troubleshoot faster and improve end-user experience. Signup Now! >> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 >> _______________________________________________ >> myhdl-list mailing list >> myh...@li... >> https://lists.sourceforge.net/lists/listinfo/myhdl-list >> . >> > > > -- > *Nicolas PINAULT > R&D electronics engineer > *** ni...@aa... <mailto:ni...@aa...> > > *AATON-Digital* > 38000 Grenoble - France > Tel +33 4 7642 9550 > > http://www.aaton.com > http://www.transvideo.eu > French Technologies for Film and Digital Cinematography > > Follow us on Twitter > @Aaton_Digital > @Transvideo_HD > > Like us on Facebook > https://www.facebook.com/AatonDigital > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Josy B. <jos...@gm...> - 2016-01-19 08:42:20
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> def dff(q,d,clk,rst): > > <at> always(clk.posedge,rst.posedge) > def logic(): > if rst==1: > q.next=0 > else: > q.next=d > > return logic > > def param_reg(q,d,clk,rst,width=4,n=2): > > signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)] > instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i > in range(n)] > > <at> always_comb > def logic(): > signal_list[0].next=d > q.next=signal_list[n+1] > > return logic,instance_list > > but I get the following error:AlwaysCombError: signal (signal_list) used > as inout in always_comb function argument > > when i change the code of param_reg to : > > def param_reg(q,d,clk,rst,width=4,n=2): > > signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)] > instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i > in range(n)] > > <at> always_comb > def logic(): > signal_list[0].next=d > <at> always_comb > def logic2(): > q.next=signal_list[n+1] > > return logic,instance_list,logic2 > > It works fine. Do you know whats the problem? This is a choice made by our BFDL. I suspect that at the time of MyHDL's initial creation it was an error (or not supported by synthesis tools) in Verilog. VHDL has no issue. I just tried a similar Verilog module with Quartus Prime, without any problem. I commented out this section in _always_comb.py: inouts = v.results['inout'] | self.inputs.intersection(self.outputs) if inouts: raise AlwaysCombError(_error.SignalAsInout % inouts) I currently don't have the time to make a PR for this ... Regards, Josy |