myhdl-list

[myhdl-list] Asynchronous double port RAM

[Nicolas P. <ni...@aa...>]

Hi,

I am experimenting with asynchronous DPR (ie : with 2 clock domains)

Here is my code :

def MemoryGene1000Hz(
                      # Port A
                      clka,
                      addra,
                      wea,
                      dia,
                      ena,
                      doa,

                      # Port B
                      clkb,
                      addrb,
                      web,
                      dib,
                      enb,
                      dob
                     ):

     data_length = len(dia)

     # Instanciate RAM array
     ram = [Signal(intbv(0)[data_length:]) for i in range(2**len(addra))]

     # Init RAM with full scale sinus (48 samples)
     scale_factor = (2**(data_length-1)) - 1
     for i in range(48) :
         v = int(sin(i*2*pi/48) * scale_factor)
         ram[i] = Signal(intbv(v)[data_length:])
         #print(i, "%6.6X" % ram[i])

     @always(clka.posedge)
     def portA():
         if ena :
             doa.next = ram[addra]
             if wea :
                 ram[addra].next = dia

     @always(clkb.posedge)
     def portB():
         if enb :
             dob.next = ram[addrb]
             if web :
                 ram[addrb].next = dib

     return portA, portB


def convert():
     from myhdl import toVHDL

     clka  = Signal(bool(0))
     addra = Signal(intbv(0)[8:])
     wea   = Signal(bool(0))
     dia   = Signal(intbv(0)[24:])
     ena   = Signal(bool(0))
     doa   = Signal(intbv(0)[24:])

     clkb  = Signal(bool(0))
     addrb = Signal(intbv(0)[8:])
     web   = Signal(bool(0))
     dib   = Signal(intbv(0)[24:])
     enb   = Signal(bool(0))
     dob   = Signal(intbv(0)[24:])

     toVHDL.directory = "../vhdl"
     #toVHDL.std_logic_ports = True
     toVHDL(MemoryGene1000Hz,
            clka,
            addra,
            wea,
            dia,
            ena,
            doa,

            clkb,
            addrb,
            web,
            dib,
            enb,
            dob
           )

The generated VHDL code is not correct.
ram array is declared as a signal while this is not correct since 2 
processes access this object.
ram array should be declared as a shared variable. Right ?

Simulation seems to be ok.

Nicolas

-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
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Re: [myhdl-list] Asynchronous double port RAM

[Josy B. <jos...@gm...>]

Nicolas Pinault <nicolas <at> aaton.com> writes:

> 
> 
>     Hi,
>     I am experimenting with asynchronous DPR (ie : with 2 clock 
domains)
>     Here is my code :
<snip>
>     The generated VHDL code is not correct. 
>     ram array is declared as a signal while this is not correct since 
2
>     processes access this object. 
>     ram array should be declared as a shared variable. Right ?
>     Simulation seems to be ok.
>     Nicolas-- 
<snip>

Hi Nicolas,

I slightly modified your code to have Quartus Prime infer a RAM :)

    @myhdl.always(clka.posedge)
    def portA():
        doa.next = ram[addra]
        if ena :
            if wea :
                ram[addra].next = dia

    @myhdl.always(clkb.posedge)
    def portB():
        dob.next = ram[addrb]
        if enb :
            if web :
                ram[addrb].next = dib
as Quartus needs a register on the output path I moved the read-
statement before the enable.

Apparently Quartus Prime has no problem with *ram* being a *signal* 
rather than a *shared variable*. Although in  the "Recommended HDL 
Coding Styles" they also show the example with a *shared variable*.

I have no idea whether Vivado and ISE are also forgiving.

Your other request: initialising the ram-array is not that much work. 
I'll try to submit a PR shortly.

Regards,

JOsy

Re: [myhdl-list] Asynchronous double port RAM

[Nicolas P. <ni...@aa...>]

Le 11/01/2016 14:26, Josy Boelen a écrit :
> Hi Nicolas,
>
> I slightly modified your code to have Quartus Prime infer a RAM :)
>
>      @myhdl.always(clka.posedge)
>      def portA():
>          doa.next = ram[addra]
>          if ena :
>              if wea :
>                  ram[addra].next = dia
>
>      @myhdl.always(clkb.posedge)
>      def portB():
>          dob.next = ram[addrb]
>          if enb :
>              if web :
>                  ram[addrb].next = dib
> as Quartus needs a register on the output path I moved the read-
> statement before the enable.
>
> Apparently Quartus Prime has no problem with *ram* being a *signal*
> rather than a *shared variable*. Although in  the "Recommended HDL
> Coding Styles" they also show the example with a *shared variable*.
>
> I have no idea whether Vivado and ISE are also forgiving.
The code I sent in my first message has been formatted following Xilinx 
rules.
However, I did not tried to compile it with Xilinx tools. I'll have a 
try and tell you.
>
> Your other request: initialising the ram-array is not that much work.
> I'll try to submit a PR shortly.
That's good news :)

Thanks
Nicolas
>
> Regards,
>
> JOsy
>
>
>
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>


-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
http://www.transvideo.eu
French Technologies for Film and Digital Cinematography

Follow us on Twitter
@Aaton_Digital
@Transvideo_HD

Like us on Facebook
https://www.facebook.com/AatonDigital

Re: [myhdl-list] Asynchronous double port RAM

[Nicolas P. <ni...@aa...>]

Le 11/01/2016 14:45, Nicolas Pinault a écrit :
> Le 11/01/2016 14:26, Josy Boelen a écrit :
>> Hi Nicolas,
>>
>> I slightly modified your code to have Quartus Prime infer a RAM :)
>>
>>      @myhdl.always(clka.posedge)
>>      def portA():
>>          doa.next = ram[addra]
>>          if ena :
>>              if wea :
>>                  ram[addra].next = dia
>>
>>      @myhdl.always(clkb.posedge)
>>      def portB():
>>          dob.next = ram[addrb]
>>          if enb :
>>              if web :
>>                  ram[addrb].next = dib
>> as Quartus needs a register on the output path I moved the read-
>> statement before the enable.
>>
>> Apparently Quartus Prime has no problem with *ram* being a *signal*
>> rather than a *shared variable*. Although in  the "Recommended HDL
>> Coding Styles" they also show the example with a *shared variable*.
>>
>> I have no idea whether Vivado and ISE are also forgiving.
> The code I sent in my first message has been formatted following 
> Xilinx rules.
> However, I did not tried to compile it with Xilinx tools. I'll have a 
> try and tell you.
Good new.
I tested with Xilinx Tools : ISE and Vivado, synthesiser/compiler and 
simulator. All configurations worked.

Regards,
Nicolas

Re: [myhdl-list] Asynchronous double port RAM

[Christopher F. <chr...@gm...>]

On 1/11/2016 7:45 AM, Nicolas Pinault wrote:

>>
>> I have no idea whether Vivado and ISE are also forgiving.
> The code I sent in my first message has been formatted following Xilinx
> rules.
> However, I did not tried to compile it with Xilinx tools. I'll have a
> try and tell you.
>>
>> Your other request: initialising the ram-array is not that much work.
>> I'll try to submit a PR shortly.
> That's good news :)


You can refer to the issue #105 for some info:
https://github.com/jandecaluwe/myhdl/issues/105

There has been some work that might be useful (or not):
https://github.com/jandecaluwe/myhdl/pull/102

Henry's first pass (see PR comments), we should limit
the feature to just "initial value" changes.
https://github.com/hgomersall/myhdl/tree/initial_value_support

I was assisting Henry some but I don't recall where I
(we) left off:
https://github.com/cfelton/myhdl/tree/initial_value_support

Regards,
Chris

Re: [myhdl-list] Asynchronous double port RAM

[Nicolas P. <ni...@aa...>]

Le 12/01/2016 15:45, Christopher Felton a écrit :
> On 1/11/2016 7:45 AM, Nicolas Pinault wrote:
>
>>> I have no idea whether Vivado and ISE are also forgiving.
>> The code I sent in my first message has been formatted following Xilinx
>> rules.
>> However, I did not tried to compile it with Xilinx tools. I'll have a
>> try and tell you.
>>> Your other request: initialising the ram-array is not that much work.
>>> I'll try to submit a PR shortly.
>> That's good news :)
>
> You can refer to the issue #105 for some info:
> https://github.com/jandecaluwe/myhdl/issues/105
>
> There has been some work that might be useful (or not):
> https://github.com/jandecaluwe/myhdl/pull/102
>
> Henry's first pass (see PR comments), we should limit
> the feature to just "initial value" changes.
> https://github.com/hgomersall/myhdl/tree/initial_value_support
>
> I was assisting Henry some but I don't recall where I
> (we) left off:
> https://github.com/cfelton/myhdl/tree/initial_value_support
Thanks for clarifying.

Regards,
Nicolas

>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
> .
>


-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
http://www.transvideo.eu
French Technologies for Film and Digital Cinematography

Follow us on Twitter
@Aaton_Digital
@Transvideo_HD

Like us on Facebook
https://www.facebook.com/AatonDigital

Re: [myhdl-list] Asynchronous double port RAM

[Henry G. <he...@ca...>]

On 12/01/16 14:45, Christopher Felton wrote:
> On 1/11/2016 7:45 AM, Nicolas Pinault wrote:
> 
>>> >>
>>> >> I have no idea whether Vivado and ISE are also forgiving.
>> > The code I sent in my first message has been formatted following Xilinx
>> > rules.
>> > However, I did not tried to compile it with Xilinx tools. I'll have a
>> > try and tell you.
>>> >>
>>> >> Your other request: initialising the ram-array is not that much work.
>>> >> I'll try to submit a PR shortly.
>> > That's good news :)
> 
> You can refer to the issue #105 for some info:
> https://github.com/jandecaluwe/myhdl/issues/105
> 
> There has been some work that might be useful (or not):
> https://github.com/jandecaluwe/myhdl/pull/102
> 
> Henry's first pass (see PR comments), we should limit
> the feature to just "initial value" changes.
> https://github.com/hgomersall/myhdl/tree/initial_value_support
> 
> I was assisting Henry some but I don't recall where I
> (we) left off:
> https://github.com/cfelton/myhdl/tree/initial_value_support

It's working*, it just needs the tests to be written. I implemented and
tested it against Vivado, which depended on an external library a wrote,
which wasn't acceptable to Jan for inclusion.

I've basically had other things that have been absorbing (literally) all
my time for quite a while. I'm likely to get back to some FPGA work
soonish though.

I think that PR suggests the suitable test scenario if you fancy a bash.

Cheers,

Henry

*it _was_ working - I haven't checked it against a recent master.