myhdl-list

[myhdl-list] YOSYS

[Edward V. <dev...@sb...>]

Hello All,https://github.com/develone/raspberrypi2_yocto/blob/master/doc/yosys_manual.pdfFrom  the yosys manual 
The proposed custom HDL synthesis tool should be licensed under a Free and Open Source Software
(FOSS) licence. So an existing FOSS Verilog or VHDL synthesis tool would have been needed as basis
to build upon. The main advantages of choosing Verilog or VHDL is the ability to synthesize existing
HDL code and to mitigate the requirement for circuit-designers to learn a new language. In order to
take full advantage of any existing FOSS Verilog or VHDL tool, such a tool would have to provide a
feature-complete implementation of the synthesizable HDL subset.
Regards
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] YOSYS

[Christopher F. <chr...@gm...>]

On 8/31/2015 2:43 PM, Edward Vidal wrote:
> Hello All,
 >
 > From the yosys manual:
 > "The proposed custom HDL synthesis tool should be
> licensed under a Free and Open Source Software (FOSS) licence. So an
> existing FOSS Verilog or VHDL synthesis tool would have been needed
> as basis to build upon. The main advantages of choosing Verilog or
> VHDL is the ability to synthesize existing HDL code and to mitigate
> the requirement for circuit-designers to learn a new language. In
> order to take full advantage of any existing FOSS Verilog or VHDL
> tool, such a tool would have to provide a feature-complete
> implementation of the synthesizable HDL subset."
 > 
https://github.com/develone/raspberrypi2_yocto/blob/master/doc/yosys_manual.pdf
 >
> Regards Edward Vidal


What in the world is this supposed to be in
context to?  Is this intended to be part of
the previous thread?  Or a post prematurely
sent?  What does it have to do with MyHDL?

Regards,
Chris

Re: [myhdl-list] YOSYS

[Edward V. <dev...@sb...>]

Chris, 
I mentioned Yosys in the co-simulation thread I just wanted to provide supporting information if you were interested.   Did not mean to offend anyone.
Regards
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 


     On Monday, August 31, 2015 1:54 PM, Christopher Felton <chr...@gm...> wrote:
   

 On 8/31/2015 2:43 PM, Edward Vidal wrote:
> Hello All,
 >
 > From the yosys manual:
 > "The proposed custom HDL synthesis tool should be
> licensed under a Free and Open Source Software (FOSS) licence. So an
> existing FOSS Verilog or VHDL synthesis tool would have been needed
> as basis to build upon. The main advantages of choosing Verilog or
> VHDL is the ability to synthesize existing HDL code and to mitigate
> the requirement for circuit-designers to learn a new language. In
> order to take full advantage of any existing FOSS Verilog or VHDL
> tool, such a tool would have to provide a feature-complete
> implementation of the synthesizable HDL subset."
 > 
https://github.com/develone/raspberrypi2_yocto/blob/master/doc/yosys_manual.pdf
 >
> Regards Edward Vidal


What in the world is this supposed to be in
context to?  Is this intended to be part of
the previous thread?  Or a post prematurely
sent?  What does it have to do with MyHDL?

Regards,
Chris



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Re: [myhdl-list] YOSYS

[Christopher F. <chr...@gm...>]

On 8/31/2015 3:03 PM, Edward Vidal wrote:
> Chris, I mentioned Yosys in the co-simulation thread I just wanted to
> provide supporting information if you were interested.   Did not mean
> to offend anyone. Regards Edward

No offense taken but I want to make sure our
communication is as efficient and clear as
possible.

Couple things, first there are numerous folks
subscribed to this mailing-list, out of courtesy we
don't want to fill peoples inboxes with too many
unrelated posts.

Second, it wasn't explicitly clear the intent (i.e.
providing additional information on ...).  The post,
from my point of view, is very confusing.  It doesn't
clearly state what yosys is (although I believe many
are familiar with it), it has a couple sentences
talking about license?  The website about [1] gives
a much better description.

Third, mentioning yosys in the co-simulation question
is actually distracting because it has nothing to do
with the issue at hand.  I realize, you intend yosys
to be part of your flow but for the cosimulation issue
it is irrelevant.

I am not suggesting the "HDL dev environment in a pi"
is interesting or not - just that some of the posts are
not particularly related to MyHDL and being a myhdl
mailing-list we should try and keep the tangents to
a minimum.

Regards,
Chris

[1] http://www.clifford.at/yosys/