myhdl-list

[myhdl-list] Avoid Latches

[Marcel H. <1he...@in...>]

Hi everyone,

currently I'm developing code for a FPGA and have the following code:

> @always_comb
> def read():
>     if ready:
>         dout.next = in_data
>         if not hit:  # tell the cache the right data, so it can store it
>             iodriverr.next = in_data

the problem is that Quartus II complains about the following:

> Warning (10240): Verilog HDL Always Construct warning at c25Board.v(358): inferring latch(es) for variable "Memory_MMU_mmuOut", which holds its previous value in one or more paths through the always construct

after talking to my prof I figured out, why this happend and how to
solve it. Just give the output a default value ('bx in verilog), but
this is not possible in myhdl, because we do not have a "undefined" or
don't care value, do we?!
So, what is the best way to solve this?! I don't like to correct this
manually in the verilog file every time.

Greetings
Marcel

Re: [myhdl-list] Avoid Latches

[Christopher F. <chr...@gm...>]

On 1/15/2014 9:57 AM, Marcel Hellwig wrote:
> Hi everyone,
>
> currently I'm developing code for a FPGA and have the following code:
>
>> @always_comb
>> def read():
>>      if ready:
>>          dout.next = in_data
>>          if not hit:  # tell the cache the right data, so it can store it
>>              iodriverr.next = in_data
>
> the problem is that Quartus II complains about the following:
>
>> Warning (10240): Verilog HDL Always Construct warning at c25Board.v(358): inferring latch(es) for variable "Memory_MMU_mmuOut", which holds its previous value in one or more paths through the always construct
>
> after talking to my prof I figured out, why this happend and how to
> solve it. Just give the output a default value ('bx in verilog), but
> this is not possible in myhdl, because we do not have a "undefined" or
> don't care value, do we?!
> So, what is the best way to solve this?! I don't like to correct this
> manually in the verilog file every time.
>
> Greetings
> Marcel
>

OT: 'x' in Verilog, is it "don't care" or is it
"unknown" or when is it one or the other :)

In an @always_comb there can be no undefined paths,
/dout/ and /iodriverr/ need to be defined for each
logical path.

If this is a bus, in an FPGA it is reasonable to
drive the bus to zero when not used, that way the
buses can be "OR'd" together.

     @always_comb
     def read():
         # default values
         dout.next = 0
         iodriverr.next = 0

         # conditional values
         if ready:
             dout.next = in_data
             if not hit:
                 iodriverr.next = in_data

This will prevent the latches.

Hope that helps,
Chris

Re: [myhdl-list] Avoid Latches

[Marcel H. <1he...@in...>]

On 15.01.2014 17:12, Christopher Felton wrote:
> OT: 'x' in Verilog, is it "don't care" or is it
> "unknown" or when is it one or the other :)
don't care :)
> In an @always_comb there can be no undefined paths,
> /dout/ and /iodriverr/ need to be defined for each
> logical path.
That's why I wanted a don't care value ;)
> If this is a bus, in an FPGA it is reasonable to
> drive the bus to zero when not used, that way the
> buses can be "OR'd" together.
I use tristates for my bus, but okay. I think that's much easier,
because I can 'switch' results on and off to the case I need them.
>      @always_comb
>      def read():
>          # default values
>          dout.next = 0
>          iodriverr.next = 0
>
>          # conditional values
>          if ready:
>              dout.next = in_data
>              if not hit:
>                  iodriverr.next = in_data
>
> This will prevent the latches.
This is one option, but iirc the reason for the don't care value is,
that the 'compiler' can optimize the output to make it as effective as
possible. But I will use the '0-solution' for now, thanks anyway.

Greetings
Marcel

Re: [myhdl-list] Avoid Latches

[Christopher F. <chr...@gm...>]

> On 15.01.2014 17:12, Christopher Felton wrote:
>> OT: 'x' in Verilog, is it "don't care" or is it
>> "unknown" or when is it one or the other :)
> don't care :)

Designer use as don't care, simulator as unknown.

>> In an @always_comb there can be no undefined paths,
>> /dout/ and /iodriverr/ need to be defined for each
>> logical path.
> That's why I wanted a don't care value ;)

See section 3 page 10 from:
http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf

>> If this is a bus, in an FPGA it is reasonable to
>> drive the bus to zero when not used, that way the
>> buses can be "OR'd" together.
> I use tristates for my bus, but okay. I think that's much easier,
> because I can 'switch' results on and off to the case I need them.

Typically, you would only use *tristates* for
off-chip interfaces.  In an FPGA or ASIC an OR'd [1]
bus or multiplexed bus would be used.

>>       @always_comb
>>       def read():
>>           # default values
>>           dout.next = 0
>>           iodriverr.next = 0
>>
>>           # conditional values
>>           if ready:
>>               dout.next = in_data
>>               if not hit:
>>                   iodriverr.next = in_data
>>
>> This will prevent the latches.
> This is one option, but iirc the reason for the don't care value is,
> that the 'compiler' can optimize the output to make it as effective as
> possible. But I will use the '0-solution' for now, thanks anyway.
>

The 'x' can cause more problems that it is worth.

Here is another paper on Verilog's 'x':
http://www.sutherland-hdl.com/papers/2013-DVCon_In-love-with-my-X_paper.pdf

Recall, Verilog is not the standard - more often it
provides examples how not to do things (sometimes
leverage the good :)

[1] really any logic the provides an "identity" can
     be used, the simple case are OR and AND
     A | 0 = A
     A & 1 = A

Regards,
Chris

Re: [myhdl-list] Avoid Latches

[Guy E. <gu...@no...>]

I like how BSV (Bluespec SystemVerilog) uses the "?" expression for 
specifying "don't care":

             if ( (a==0) && (b==0) )
                o = 1;
             else if ( (a==1) && (b==1) )
                o = 0;
             else
                o = ?;

Since BSV uses 2-valued logic, the "?" does not mean 'X'. It just allows 
the compiler to pick whatever value it thinks is more convenient.

Cheers,
Guy.


Am 16.01.2014 15:43, schrieb Christopher Felton:
>> On 15.01.2014 17:12, Christopher Felton wrote:
>>> OT: 'x' in Verilog, is it "don't care" or is it
>>> "unknown" or when is it one or the other :)
>> don't care :)
> Designer use as don't care, simulator as unknown.
>
>>> In an @always_comb there can be no undefined paths,
>>> /dout/ and /iodriverr/ need to be defined for each
>>> logical path.
>> That's why I wanted a don't care value ;)
> See section 3 page 10 from:
> http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf
>
>>> If this is a bus, in an FPGA it is reasonable to
>>> drive the bus to zero when not used, that way the
>>> buses can be "OR'd" together.
>> I use tristates for my bus, but okay. I think that's much easier,
>> because I can 'switch' results on and off to the case I need them.
> Typically, you would only use *tristates* for
> off-chip interfaces.  In an FPGA or ASIC an OR'd [1]
> bus or multiplexed bus would be used.
>
>>>        @always_comb
>>>        def read():
>>>            # default values
>>>            dout.next = 0
>>>            iodriverr.next = 0
>>>
>>>            # conditional values
>>>            if ready:
>>>                dout.next = in_data
>>>                if not hit:
>>>                    iodriverr.next = in_data
>>>
>>> This will prevent the latches.
>> This is one option, but iirc the reason for the don't care value is,
>> that the 'compiler' can optimize the output to make it as effective as
>> possible. But I will use the '0-solution' for now, thanks anyway.
>>
> The 'x' can cause more problems that it is worth.
>
> Here is another paper on Verilog's 'x':
> http://www.sutherland-hdl.com/papers/2013-DVCon_In-love-with-my-X_paper.pdf
>
> Recall, Verilog is not the standard - more often it
> provides examples how not to do things (sometimes
> leverage the good :)
>
> [1] really any logic the provides an "identity" can
>       be used, the simple case are OR and AND
>       A | 0 = A
>       A & 1 = A
>
> Regards,
> Chris
>
>
>
>
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Re: [myhdl-list] Avoid Latches

[Christopher F. <chr...@gm...>]

On 1/16/2014 11:15 AM, Guy Eschemann wrote:
>
> I like how BSV (Bluespec SystemVerilog) uses the "?" expression for
> specifying "don't care":
>
>               if ( (a==0) && (b==0) )
>                  o = 1;
>               else if ( (a==1) && (b==1) )
>                  o = 0;
>               else
>                  o = ?;


The use of '?' in V/SV is the recommended don't
care for /casez/ statements.  The use of 'x' as a
don't care is a hijacking of the of the definition
(IMO).

But in general, I am not convinced a don't care is
needed at the HDL level.  I think there is a difference
between representing a logical function syntactically
in an HDL vs minimizing a logic expression with inputs
and outputs defined as "don't cares".

In other words, we know logic optimization works great
with simple input output tables but not necessarily
with conditional type descriptions.  It might be the
case we can simplify the HDL description if we don't
even consider don't cares.

     o.next = False if a and b else True
     # which is "not (a and b)"

Regards,
Chris