myhdl-list

[myhdl-list] emulate always_seq decorator

[Marcel H. <1he...@in...>]

Hi everyone,

one of my devices is using yield a lot (state machine), but the
decorators don't support generator functions. So I looked up in the
source and wrote my own 'always_seq' decorator.

> @instance
>     def genFunction():
>         #we emulate a @always_seq(clk.posedge)
>         senslist = [clk.posedge]
> 
>         if reset.async:
>             if reset.active:
>                 senslist.append(reset.posedge)
>             else:
>                 senslist.append(reset.negedge)
> 
>         while True:
>             yield senslist
> 
>             if reset == reset.active:
>                 presetSignals()
>                 state.next = tState.FETCH
>             else:
>                 yield logic()


the problem is, that toVHDL is now complaining about a lof ot things

> myhdl.ConversionError: in file /home/marcel/studium/WISE1314/Projekt/hardware/cpu.py, line 254:
>     Not supported: list
this is the senslist = [clk.posedge] line. And also
> myhdl.ConversionError: in file /home/marcel/studium/WISE1314/Projekt/hardware/cpu.py, line 266:
>     Unsupported attribute: active

(if reset == reset.active).

How do I tell myhdl that he should translate this as usual?! Or tell me
a different method to use yield inside a always_seq decorated function.

Greetings,
Marcel

Re: [myhdl-list] emulate always_seq decorator

[Jan D. <ja...@ja...>]

On 12/27/2013 09:01 AM, Marcel Hellwig wrote:
> Hi everyone,
>
> one of my devices is using yield a lot (state machine), but the
> decorators don't support generator functions.

The @instance decorator does. Why not simply use that?

Also, dynamic sensitivity lists are not supported in conversion.

Jan

  So I looked up in the
> source and wrote my own 'always_seq' decorator.
>
>> @instance
>>      def genFunction():
>>          #we emulate a @always_seq(clk.posedge)
>>          senslist = [clk.posedge]
>>
>>          if reset.async:
>>              if reset.active:
>>                  senslist.append(reset.posedge)
>>              else:
>>                  senslist.append(reset.negedge)
>>
>>          while True:
>>              yield senslist
>>
>>              if reset == reset.active:
>>                  presetSignals()
>>                  state.next = tState.FETCH
>>              else:
>>                  yield logic()
>
>
> the problem is, that toVHDL is now complaining about a lof ot things
>
>> myhdl.ConversionError: in file /home/marcel/studium/WISE1314/Projekt/hardware/cpu.py, line 254:
>>      Not supported: list
> this is the senslist = [clk.posedge] line. And also
>> myhdl.ConversionError: in file /home/marcel/studium/WISE1314/Projekt/hardware/cpu.py, line 266:
>>      Unsupported attribute: active
>
> (if reset == reset.active).
>
> How do I tell myhdl that he should translate this as usual?! Or tell me
> a different method to use yield inside a always_seq decorated function.
>
> Greetings,
> Marcel
>
>
>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] emulate always_seq decorator

[Marcel H. <ke...@co...>]

On 27.12.2013 17:25, Jan Decaluwe wrote:
> On 12/27/2013 09:01 AM, Marcel Hellwig wrote:
>> Hi everyone,
>>
>> one of my devices is using yield a lot (state machine), but the
>> decorators don't support generator functions.
> 
> The @instance decorator does. Why not simply use that?
> 
> Also, dynamic sensitivity lists are not supported in conversion.
> 
> Jan
As you might see, I use @instance atm. But the problem is, that I have a
reset signal and a clk signal, I want to use them both. But how does the
orignal always_seq is translated to vhdl code?
Also, why is there the restriction, that you cannot use a generator
function for @always... ?

Marcel

Re: [myhdl-list] emulate always_seq decorator

[Jan D. <ja...@ja...>]

On 12/27/2013 07:54 PM, Marcel Hellwig wrote:

> As you might see, I use @instance atm. But the problem is, that I have a
> reset signal and a clk signal, I want to use them both.

The yield statement is general:

http://www.myhdl.org/doc/current/manual/reference.html#myhdl-generators-and-trigger-objects

> Also, why is there the restriction, that you cannot use a generator
> function for @always... ?

Python generator functions are quite different than
normal functions in terms of behavior and usage.

Moreover, I don't think mixing implicit sensitity (in
an arguent list of a decorator) with explicit
sensitivity (with yield) is a good concept. This
concept is the same in VHDL.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com