myhdl-list

Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Christopher F. <chr...@gm...>]

On 5/3/12 4:03 PM, Jan Decaluwe wrote:
> On 05/03/2012 06:30 PM, Christopher Lozinski wrote:
>>
>>>> My mistake.  It is easy to think of MyHDL as a shared project with
>>>> people having shared direction.  And then we get to discuss the shared
>>>> direction.  The reality is that each person does whatever they want.
>>>> Thank you for clearing up my understanding of open source projects.
>>
>>> Christopher, it sounds like you are being sarcastic here but if so in fact
>>> you really are mistaken about what happens in open source projects with no
>>> paid engineers.  The purpose of discussion is only to give a person ideas.
>>> That person will then go off and do whatever they want.  And whether that
>>> gets back into the main tree is entirely up to the owners of the project,
>>> who will do whatever they want with the submission :-).  If they don't take
>>> it you may get a fork...
>> Actually I was not being sarcastic.  I did not quite understand the
>> culture of open source projects.  Thank you for clearing that up.
>
> May I remind you and others that you certainly understand
> the "each person does whatever they want" part.
>
> A few weeks ago, you said that you preferred Migen, because you judged that
> you only needed concurrent statements. Just a few days ago, you gave
> us your final thoughts before moving to Verilog.
>
> I am personally all in favor of "doing whatever you want". But
> you can not expect that someone that jumps around has equal
> say in the "shared direction" of a project as those who are truly
> committed to it. That should be obvious.
>

Amen to that!

Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Christopher L. <loz...@fr...>]

On 5/3/12 8:14 PM, Christopher Felton wrote:
>> I am personally all in favor of "doing whatever you want". But
>> > you can not expect that someone that jumps around has equal
>> > say in the "shared direction" of a project as those who are truly
>> > committed to it. That should be obvious.
>> >
> Amen to that!
Be tough on issues, soft on people. 

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] How to make MyHDL Object-Oriented

[Tom D. <td...@di...>]

It seems to me we are just being drawn into ridiculous conversations.

I am more productive with MyHDL/Python and Verilog/VHDL that with only 
straight Verilog/VHDL, so I use it.

Particularly for test benches and re-usable IP modules. I would suggest 
to anyone who wants to learn the benefits of MyHDL, that begin with test 
benches. It is a great way to increase your test coverage and do it in 
far less time than with an HDL test bench.

After some experience is gained using MyHDL, your comments about what 
can and can't be done with it might be more useful to the list.

Right now debating whether or not you can use classes is absurd.



On 05/04/2012 07:18 AM, Christopher Lozinski wrote:
> On 5/4/12 5:04 AM, Jan Decaluwe wrote:
>> On 05/04/2012 01:45 AM, Christopher Lozinski wrote:
>>> Thanks enormously to Andy Stone for pointing out that MyHDL, while in
>>> Python is not object-oriented.  There is no hardware module class, just
>>> a generator, and decorator which are functional approaches.
>> How can you even say this,
>
> Actually the wiki says it.
>
> http://www.myhdl.org/doc/0.6/manual/intro.html
> In MyHDL, classic functions are used to model hardware modules. In 
> particular, the parameter list is used to define the interface.
>
> I would rather see objects being used to model hardware modules.  In 
> particular the instance variables should be used to model the 
> interface.  (and internal signals).
>
> Here is another one.
> http://www.myhdl.org/doc/current/manual/modeling.html
>
> In MyHDL, an instance is recursively defined as being either a 
> sequence of instances, or a generator. Hierarchy is modeled by 
> defining instances in a higher-level function, and returning them.
>
> That does sound to me like a functional approach.  I would rather see 
> hardware modules defined "in a higher level object" a module with 
> parent and child nodes.
> I would expect a hierarchy of chip modules, each of which points to 
> its children and parents.
>
> Then let me quote others: Andrew Stone said this is what he expected:
>
>     In fact, what I thought myHDL was going to let me do is create
>     classes that define blocks of logic at the RTL level
>     (synthesizable), perhaps with inputs and output "Signals" as
>     variables passed in the constructor and then by instantiating
>     those classes I'd be in effect plunking down copies of that logic
>     in the FPGA (or within larger logic blocks by instantiating these
>     within the constructor of another class).  4 years ago I did not
>     ever figure out how to do this... I don't think anything wrapped
>     in a class was synthesizable back then.  But maybe that has
>     changed now; I haven't tried using classes since.
>
> And yes, Dillon wrote that he does this, but I think we will find the 
> details of how he does it are different than at least what I would 
> expect.  In particular MyHDL does not pass variables into the object 
> constructor, it passes them into the generator.  There are no parent 
> or child links.
>
>
>> when the manual has a section about
>> object-oriented modeling, which has a Queue class, which you have
>> just been struggling with?
>
> If I recall correctly, the Queue class is not inside a @always, 
> @instance, or @always_comb, so it is not synthesizable.  While MyHDL 
> is quite general, it is only the synthesizable stuff I am interested in.
>
>
> Jan Decaluwe wrote:
>
> >Perhaps this stuff really is too hard for the "general python developer", though I
>
> >still don't understand why.
> Because it does not fit the way we see the world.   Different people 
> have different world views.  I am doing my best to explain my world 
> view.  In particular one of my concepts is that every real world thing 
> should be represented by a class.  So flip flops, adders, multipliers 
> should each be represented by a class.  And then I mostly want the 
> documentation to be a listing of the classes, representing physical 
> objects,  available to me to work with.  And yes the existing MyHDL 
> documentation would also be useful.
>
> I now understand it is a hugely different view from the prevailing 
> view on this mailing list.   And that is why we keep clashing.  It is 
> why I am just not able to 'get' MyHDL.  Because we are operating under 
> two different world views.
>
> -- 
> Regards
> Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift.
> http://MyHDL.org
>
>
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Re: [myhdl-list] How to make MyHDL Object-Oriented

[Christopher F. <chr...@gm...>]

On 5/4/12 8:34 AM, Tom Dillon wrote:
> It seems to me we are just being drawn into ridiculous conversations.
>
> I am more productive with MyHDL/Python and Verilog/VHDL that with only
> straight Verilog/VHDL, so I use it.
>
> Particularly for test benches and re-usable IP modules. I would suggest
> to anyone who wants to learn the benefits of MyHDL, that begin with test
> benches. It is a great way to increase your test coverage and do it in
> far less time than with an HDL test bench.
>
> After some experience is gained using MyHDL, your comments about what
> can and can't be done with it might be more useful to the list.
>
> Right now debating whether or not you can use classes is absurd.
>
>

+1 Tom has many good point here!

Re: [myhdl-list] How to make MyHDL Object-Oriented

[garyr <ga...@fi...>]

----- Original Message ----- 
From: "Tom Dillon" <td...@di...>
To: <myh...@li...>
Sent: Friday, May 04, 2012 7:40 AM
Subject: Re: [myhdl-list] How to make MyHDL Object-Oriented


> Hardly an attack.
> 
> I fail to see the issue to be hard on.

Amen to that. Crackpots shouldn't expect sympathy.