myhdl-list

[myhdl-list] bidirectional bus -tristate help

[Tom F. <fit...@gm...>]

Hello,
I know this topic has been discussed before, but I still do not
understand it. I am trying to make a bidirectional bus for an external
sram. I can't figure out how to use TristateSignal.

I have di (data in) , do (data out) , ld (latch data) , and read. When
read is on I want latch_data to be read to data_in and when it is
off I want di to be written to the latch_data. Here is what I have:

from myhdl import *
from random import randrange

def Buffer(do, di, ld, read):

     buff = TristateSignal(intbv(0)[16:])
     driver1 = buff.driver()
     driver2 = buff.driver()

     @always_comb
     def logic():
         if read == 0:
             driver1.next = do.val
             ld.next = driver1.val
             driver2.next = None
         else:
              driver1.next = None
              driver2.next = ld.val
             di.next = driver2.val

      return logic

ld = TristateSignal(intbv(0)[16:])
do, di = [Signal(intbv(0)[16:]) for i in range(2)]
clock, read = [Signal(bool(0)) for i in range(2)]

tristate_buf_inst = Buffer(do, di, ld, read)

def test_tristate():

     @always(delay(10))
     def clkgen():
         clock.next = not clock

     @instance
     def stimulus():
         ram = [ ] # holds random values generated during writing stage

         print "Writing"
         print "now", "do", "di", "ld"

         for i in range(5):
             data = randrange(255)
             do.next = data
             ram.append(data)
             yield clock.negedge

         print "Reading"
         print "now", "q_do", "di", "ld"
         for i in range(5):
             read.next = 1
             ld.next = ram[i]
             yield delay(10)

         raise StopSimulation

     @always(clock.negedge)
     def monitor():
         print now(), do, di, ld

     return tristate_buf_inst, clkgen, stimulus, monitor

sim = Simulation(test_tristate())
sim.run()

This raises an error that ld is being used as an inout signal. I've done variations on this and was able to
pipe data from do to ld, but not from ld to di by making ld a tristate. How do I configure the bridge (tristate)
to deliver data correctly when I can only set one end? Should ld be the tristate since it is the only inout
signal? If so, how do I set ld in my test in order to pipe data from ld to di?

Any help is welcome. Thank you for your time and consideration.

Re: [myhdl-list] bidirectional bus -tristate help

[Christopher F. <chr...@gm...>]

On 12/14/2011 8:24 PM, Tom Fitz wrote:
>
> Hello,
> I know this topic has been discussed before, but I still do not
> understand it. I am trying to make a bidirectional bus for an external
> sram. I can't figure out how to use TristateSignal.
>

If you have not reviewed this MEP, 
http://www.myhdl.org/doku.php/meps:mep-105, it is worthwhile reviewing 
to get more background on the latest TriState (ShadowSignal) implementation.

I will gladly look over your posted code but it will be a couple days 
(maybe even a week) before I can get to it.

Regards,
Chris

Re: [myhdl-list] bidirectional bus -tristate help

[Tom F. <fit...@gm...>]

On 12/15/2011 4:35 AM, Christopher Felton wrote:
> On 12/14/2011 8:24 PM, Tom Fitz wrote:
>> Hello,
>> I know this topic has been discussed before, but I still do not
>> understand it. I am trying to make a bidirectional bus for an external
>> sram. I can't figure out how to use TristateSignal.
>>
> If you have not reviewed this MEP,
> http://www.myhdl.org/doku.php/meps:mep-105, it is worthwhile reviewing
> to get more background on the latest TriState (ShadowSignal) implementation.
>
> I will gladly look over your posted code but it will be a couple days
> (maybe even a week) before I can get to it.
>
> Regards,
> Chris
>
>
> ------------------------------------------------------------------------------
> 10 Tips for Better Server Consolidation
> Server virtualization is being driven by many needs.
> But none more important than the need to reduce IT complexity
> while improving strategic productivity.  Learn More!
> http://www.accelacomm.com/jaw/sdnl/114/51507609/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
Thank you. Anything helps, even a better explanation of the concepts. I 
had already read that page, but it did give so new insights this time 
around. I understand how to use vanilla shadow signals, but I can't 
figure out tristates. I'll keep working at it and post my progress. 
Thanks again.

Re: [myhdl-list] bidirectional bus -tristate help

[Norbo <Nor...@gm...>]

Am 15.12.2011, 03:24 Uhr, schrieb Tom Fitz <fit...@gm...>:

>
> Hello,
> I know this topic has been discussed before, but I still do not
> understand it. I am trying to make a bidirectional bus for an external
> sram. I can't figure out how to use TristateSignal.
>
> I have di (data in) , do (data out) , ld (latch data) , and read. When
> read is on I want latch_data to be read to data_in and when it is
> off I want di to be written to the latch_data. Here is what I have:
>
> from myhdl import *
> from random import randrange
>
> def Buffer(do, di, ld, read):
>
>      buff = TristateSignal(intbv(0)[16:])
>      driver1 = buff.driver()
>      driver2 = buff.driver()
>
>      @always_comb
>      def logic():
>          if read == 0:
>              driver1.next = do.val
>              ld.next = driver1.val
>              driver2.next = None
>          else:
>               driver1.next = None
>               driver2.next = ld.val
>              di.next = driver2.val
>
>       return logic
>
> ld = TristateSignal(intbv(0)[16:])
> do, di = [Signal(intbv(0)[16:]) for i in range(2)]
> clock, read = [Signal(bool(0)) for i in range(2)]
>
> tristate_buf_inst = Buffer(do, di, ld, read)
>
> def test_tristate():
>
>      @always(delay(10))
>      def clkgen():
>          clock.next = not clock
>
>      @instance
>      def stimulus():
>          ram = [ ] # holds random values generated during writing stage
>
>          print "Writing"
>          print "now", "do", "di", "ld"
>
>          for i in range(5):
>              data = randrange(255)
>              do.next = data
>              ram.append(data)
>              yield clock.negedge
>
>          print "Reading"
>          print "now", "q_do", "di", "ld"
>          for i in range(5):
>              read.next = 1
>              ld.next = ram[i]
>              yield delay(10)
>
>          raise StopSimulation
>
>      @always(clock.negedge)
>      def monitor():
>          print now(), do, di, ld
>
>      return tristate_buf_inst, clkgen, stimulus, monitor
>
> sim = Simulation(test_tristate())
> sim.run()
>
> This raises an error that ld is being used as an inout signal. I've done  
> variations on this and was able to
> pipe data from do to ld, but not from ld to di by making ld a tristate.  
> How do I configure the bridge (tristate)
> to deliver data correctly when I can only set one end? Should ld be the  
> tristate since it is the only inout
> signal? If so, how do I set ld in my test in order to pipe data from ld  
> to di?
>
> Any help is welcome. Thank you for your time and consideration.



Is it something like this you wanted to do? i wasnt so sure because in the  
text
you were talking about di but in the code there was a do??



 from myhdl import *
 from random import randrange

def Buffer(do, di, ld, read):

      buff = TristateSignal(intbv(0)[16:])
      driver1 = buff.driver()
      driver2 = buff.driver()

      @always_comb
      def logic():
          if read == 0:
              ld.next = do.val

      @always_comb
      def logic2():
	 if read == 1:
              di.next = ld.val

      return logic,logic2

ld = Signal(intbv(0)[16:])
do, di = [Signal(intbv(0)[16:]) for i in range(2)]
clock, read = [Signal(bool(0)) for i in range(2)]

tristate_buf_inst = Buffer(do, di, ld, read)

def test_tristate():

      @always(delay(10))
      def clkgen():
          clock.next = not clock

      @instance
      def stimulus():
          ram = [ ] # holds random values generated during writing stage

          print "Writing"
          print "now", "do", "di", "ld"

          for i in range(5):
              data = randrange(255)
              do.next = data
              ram.append(data)
              yield clock.negedge
	
	 yield clock.posedge
          print "Reading"
          print "now", "q_do", "di", "ld"
          for i in range(5):
              read.next = 1
              ld.next = ram[i]
              yield clock.negedge #yield delay(10)

          raise StopSimulation

      @always(clock.negedge)
      def monitor():
          print now(), do, di, ld

      return tristate_buf_inst, clkgen, stimulus, monitor

sim = Simulation(test_tristate())
sim.run()

Re: [myhdl-list] bidirectional bus -tristate help

[Tom F. <fit...@gm...>]

On 12/15/2011 2:23 PM, Norbo wrote:
> Am 15.12.2011, 03:24 Uhr, schrieb Tom Fitz<fit...@gm...>:
>
>> Hello,
>> I know this topic has been discussed before, but I still do not
>> understand it. I am trying to make a bidirectional bus for an external
>> sram. I can't figure out how to use TristateSignal.
>>
>> I have di (data in) , do (data out) , ld (latch data) , and read. When
>> read is on I want latch_data to be read to data_in and when it is
>> off I want di to be written to the latch_data. Here is what I have:
>>
>> from myhdl import *
>> from random import randrange
>>
>> def Buffer(do, di, ld, read):
>>
>>       buff = TristateSignal(intbv(0)[16:])
>>       driver1 = buff.driver()
>>       driver2 = buff.driver()
>>
>>       @always_comb
>>       def logic():
>>           if read == 0:
>>               driver1.next = do.val
>>               ld.next = driver1.val
>>               driver2.next = None
>>           else:
>>                driver1.next = None
>>                driver2.next = ld.val
>>               di.next = driver2.val
>>
>>        return logic
>>
>> ld = TristateSignal(intbv(0)[16:])
>> do, di = [Signal(intbv(0)[16:]) for i in range(2)]
>> clock, read = [Signal(bool(0)) for i in range(2)]
>>
>> tristate_buf_inst = Buffer(do, di, ld, read)
>>
>> def test_tristate():
>>
>>       @always(delay(10))
>>       def clkgen():
>>           clock.next = not clock
>>
>>       @instance
>>       def stimulus():
>>           ram = [ ] # holds random values generated during writing stage
>>
>>           print "Writing"
>>           print "now", "do", "di", "ld"
>>
>>           for i in range(5):
>>               data = randrange(255)
>>               do.next = data
>>               ram.append(data)
>>               yield clock.negedge
>>
>>           print "Reading"
>>           print "now", "q_do", "di", "ld"
>>           for i in range(5):
>>               read.next = 1
>>               ld.next = ram[i]
>>               yield delay(10)
>>
>>           raise StopSimulation
>>
>>       @always(clock.negedge)
>>       def monitor():
>>           print now(), do, di, ld
>>
>>       return tristate_buf_inst, clkgen, stimulus, monitor
>>
>> sim = Simulation(test_tristate())
>> sim.run()
>>
>> This raises an error that ld is being used as an inout signal. I've done
>> variations on this and was able to
>> pipe data from do to ld, but not from ld to di by making ld a tristate.
>> How do I configure the bridge (tristate)
>> to deliver data correctly when I can only set one end? Should ld be the
>> tristate since it is the only inout
>> signal? If so, how do I set ld in my test in order to pipe data from ld
>> to di?
>>
>> Any help is welcome. Thank you for your time and consideration.
>
>
> Is it something like this you wanted to do? i wasnt so sure because in the
> text
> you were talking about di but in the code there was a do??
>
>
>
>   from myhdl import *
>   from random import randrange
>
> def Buffer(do, di, ld, read):
>
>        buff = TristateSignal(intbv(0)[16:])
>        driver1 = buff.driver()
>        driver2 = buff.driver()
>
>        @always_comb
>        def logic():
>            if read == 0:
>                ld.next = do.val
>
>        @always_comb
>        def logic2():
> 	 if read == 1:
>                di.next = ld.val
>
>        return logic,logic2
>
> ld = Signal(intbv(0)[16:])
> do, di = [Signal(intbv(0)[16:]) for i in range(2)]
> clock, read = [Signal(bool(0)) for i in range(2)]
>
> tristate_buf_inst = Buffer(do, di, ld, read)
>
> def test_tristate():
>
>        @always(delay(10))
>        def clkgen():
>            clock.next = not clock
>
>        @instance
>        def stimulus():
>            ram = [ ] # holds random values generated during writing stage
>
>            print "Writing"
>            print "now", "do", "di", "ld"
>
>            for i in range(5):
>                data = randrange(255)
>                do.next = data
>                ram.append(data)
>                yield clock.negedge
> 	
> 	 yield clock.posedge
>            print "Reading"
>            print "now", "q_do", "di", "ld"
>            for i in range(5):
>                read.next = 1
>                ld.next = ram[i]
>                yield clock.negedge #yield delay(10)
>
>            raise StopSimulation
>
>        @always(clock.negedge)
>        def monitor():
>            print now(), do, di, ld
>
>        return tristate_buf_inst, clkgen, stimulus, monitor
>
> sim = Simulation(test_tristate())
> sim.run()
>
>
> ------------------------------------------------------------------------------
> 10 Tips for Better Server Consolidation
> Server virtualization is being driven by many needs.
> But none more important than the need to reduce IT complexity
> while improving strategic productivity.  Learn More!
> http://www.accelacomm.com/jaw/sdnl/114/51507609/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Wow. Thank you so much. I swear I had tried that, but maybe I wrote my 
test the wrong way. That's amazing. I was really barking up the wrong 
tree with the tristates. I think the essential thing I missed was using 
always_comb's in my initial attempts.