Thread: [myhdl-list] myHDL First Project: Audio Effects System

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I want to attack a useful stand-alone application as my first myHDL project, with the primary goal being to become intimately familiar with all aspects of the myHDL-to-hardware development process (making full use of the expertise captured on the myHDL site), and the secondary goal being to start learning digital design by examining the work of others and porting it to myHDL.

To the greatest extent possible, code will be released under an appropriate Open license on OpenCores, GitHub and/or the myHDL site.

I've chosen to implement an audio effects suite that would initially be suitable for use as a guitar pedal system or voice processor.  I have the following specific goals:

A. General specifications/scope:
  - Support line-level analog input and output.
  - Start with 44.1 KHz audio sample rate, sample width of ~10 bits.
  - Design should be parameterized for faster/wider analog data.
  - Allow for future resampling to support different input and output sample rates/widths.
  - Start with single audio channel I/O.
  - Allow for upgrades for multiple input and output channels and mixing.
  - Modular design for individual effects with a common streaming interface.
  - Effects built from a set of reusable mathematical/operational elements.
  - Allow for implementation optimizations to mux operating elements in time domain.
- Start with simple effects (echo, reverb, filtering).
  - Allow for more complex effects (e.g., pitch modification, auto-tune).
  - Start with a simple discrete button control interface.
  - Allow for multiple control interfaces: MIDI, SPI, parallel.
  - Allow for use by internal uP (e.g. http://opencores.org/project,avr_core)
  - Start with simple discrete LED status/configuration display.
  - Allow for output of current status/configuration (serial, parallel).
  - Allow for tracking net delay between input and output (effects modules would eventually need to report the delay they currently add to the process).
  - Allow for future inclusion of a VGA display (control, status, animated effects)

B. Implementation constraints:
  - Initial hardware target is a Spartan 3E-500-4 FPGA with external SRAM available.
  - My initial dev board: http://www.kickstarter.com/projects/794668827/aliencortex-av
  - Use PWM on a standard digital output with RC filter to implement a 44.1 KHz ~10-bit DAC.
  - Use an LVDS comparator to implement a successive-approximation or sigma-delta 44.1 KHz ~10-bit ADC.
  - Allow for future use of external ADCs/DACs (SPI, parallel) and other streaming data sources (PC, S/PDIF).

I have several reasons for choosing this project:
  - It's useful and fun.
  - It is relatively easy to understand.
  - It is a stand-alone system (minimal parts needed other than FPGA itself).
  - It is a true SoC, but a fairly simple one.
- It can be expanded almost without limit.
  - Data rates are slow enough to monitor with inexpensive equipment (PC, multimeter).
  - Real-time simulation/emulation possible with even slow PCs.
  - Relevant software and Verilog/VHDL code snippets are freely available, permitting initial development to focus more on architecture and process rather than detailed digital design.
  - Opportunities for cosimulation and mixed-signal simulation (Spice for external analog components).
  - Could eventually become an end-to-end myHDL hands-on tutorial.
  - Should be compatible with broad community participation.

I expect the system will have multiple implementation/elaboration cycles, starting with simple (perhaps inefficient) and progressing to sophisticated and highly optimized.  For example:
  - Implement DAC using PWM first, successive-approximation later.
  - Test DAC with canned data and multimeter (DC) or o'scope (AC).
  - Implement digital ADC using LVDS comparator: successive-approximation first, delta-sigma later.
  - Test ADC with resistor ladder (DC tests).
- Do Spice analog cosimulation of external components of ADC and DAC (optional).
  - Connect ADC input to DAC output.
  - Connect microphone and earbuds, test 'live'.
  - Measure delay between input and output.
  - Add fixed echo effect.
  - Test as isolated component.
  - Integrate with ADC/DAC.
  - Test as system.
  - Modify echo module and tests to support variable echo delay and decay times.
  - Use buttons to control echo module, and discrete LEDs to display state.
  - Add hiss (low-pass) filter effect.
  - Test in isolation.
  - Test as integrated system.
  - Test via cosimulation (optional).
  - Add mux/switch component to select effects and their order.
  - Update modules to use uniform streaming and control interfaces.
  - Add RS-232 status/control interface (for use by a person with a terminal program).
- Add more effects:
     - Import other HDL code (e.g. FIR filter) into a myHDL wrapper.
     - Add myHDL tests.
     - Port code from other HDL to myHDL.
  - Add SPI interface for use by external uP (make it look more like just another part).
- Add subsystem reuse in time domain (with state switching).
- Add basic VGA display.
  - Convert from a stand-alone component to a core.
  - Add AVR8 core (or, more correctly, add effects system as AVR8 peripheral on SoC).
  - Add software for more sophisticated and flexible operation (e.g., simpler external control).  (I really wish the embedded core could run Python...)

While the project goals are initially based on my own desires, I hope this project could eventually become an ideal gateway tutorial project for myHDL, since it creates a real product (not a toy example) that starts simple (and fully functional) and grows to a complete SoC, while hopefully requiring only minimal resources (few components, simple tools, no logic analyzer) and limited digital design skills (e.g., no SDRAM interface).

Before going any further, I'd like to solicit suggestions and recommendations from the myHDL community:

1. Would you be interested in supporting this project with mentoring, infrastructure, and/or code?

2. I think I'd like to document project progress on a wiki.  Recommendations?  Alternatives?  Should I use a page on the myHDL wiki?  Or would a blog be better (possibly with a wiki)?

3. Is it OK to use the myHDL list as a forum for this project, or should it get its own facilities?

4. What is this project missing?

Thanks,

-BobC