myhdl-list

[myhdl-list] Control over output file generation

[Eric J. <jo...@MI...>]

Hello! MyHDL has been a lot of fun thus far, but as I look toward
automating more of my design flow, I'm stuck on one question: The
correct way to control both the location and name of the generated
verilog/vhdl code. 

In particular, how do I tell toVerilog() to dump the output file
in /foo/bar/baz.v?  And is it at all possible to control the filenames
that the different contained modules will be generated as? I have some
code analysis and automated build tools that I'm trying to interoperate
with. 

Thanks again, 
		...Eric

Re: [myhdl-list] Control over output file generation

[Günter D. <dan...@we...>]

Eric Jonas wrote:
> Hello! MyHDL has been a lot of fun thus far, but as I look toward
> automating more of my design flow, I'm stuck on one question: The
> correct way to control both the location and name of the generated
> verilog/vhdl code. 

The file name in connection with the module name can be changed with the
toVerilog.name or toVHDL.name attribute. See the reference document for
that:

http://www.myhdl.org/doc/0.6/manual/reference.html#myhdl.toVerilog
http://www.myhdl.org/doc/0.6/whatsnew/0.6.html#toVHDL

Now I am not sure whether that would also allow to add a path. You might
have to do some additional Python tricks to do that.

My first idea was to just do a os.chdir() ahead of the toVerilog/toVHDL
call, but that might not work as the converter will not find the code
then. Easiest way might be to create the code and then move it with a
combination of shutil.copy() and os.remove() to the path you want.

Cheers,

Guenter

Re: [myhdl-list] Control over output file generation

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:
> Eric Jonas wrote:
>> Hello! MyHDL has been a lot of fun thus far, but as I look toward
>> automating more of my design flow, I'm stuck on one question: The
>> correct way to control both the location and name of the generated
>> verilog/vhdl code. 
> 
> The file name in connection with the module name can be changed with the
> toVerilog.name or toVHDL.name attribute. See the reference document for
> that:
> 
> http://www.myhdl.org/doc/0.6/manual/reference.html#myhdl.toVerilog
> http://www.myhdl.org/doc/0.6/whatsnew/0.6.html#toVHDL
> 
> Now I am not sure whether that would also allow to add a path. You might
> have to do some additional Python tricks to do that.

No, .name merely changes the top level design name from its default.
The name is also used to define a filename, but that cannot be
further controlled at this point.

I guess we should add an additional attribute (.filename ?) to
control the desired filename.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org