myhdl-list

[myhdl-list] [new] design flow question

[Neal B. <ndb...@gm...>]

I know only a little about Verilog - I do algorithm development and hand off to coworkers who produce verilog.

We typically do a lot of DSP work (lots of arithmetic).  Often, things like Xylinx cores are used.

Would that sort of design flow work with a myhdl frontend?  Any hints?

Re: [myhdl-list] [new] design flow question

[Felton C. <chr...@gm...>]

On the website there are many examples, check out some of the  
following links.

http://www.myhdl.org/doku.php/publications  -- This is your one stop  
shop, the paper by Dillon Engineering (a bunch of active MyHDL  
contributors) describes exactly what you are looking for (http://www.myhdl.org/doku.php/publications 
).

Different examples that have been contributed to the site
http://www.myhdl.org/doku.php/cookbook:sinecomp   -- Implementation of  
the cordic
http://www.myhdl.org/doku.php/cookbook:bitonic   	-- Sort algorithm  
implementation
http://www.myhdl.org/doku.php/projects:cordic_calculations	-- Another  
cordic
http://www.myhdl.org/doku.php/projects:gcicexample	-- CIC Filter
http://www.myhdl.org/doku.php/projects:conste_encoder  --  
Constellation Encoder

Good luck


On Dec 17, 2008, at 7:34 PM, Neal Becker wrote:

> I know only a little about Verilog - I do algorithm development and  
> hand off to coworkers who produce verilog.
>
> We typically do a lot of DSP work (lots of arithmetic).  Often,  
> things like Xylinx cores are used.
>
> Would that sort of design flow work with a myhdl frontend?  Any hints?
>
>
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[myhdl-list] MICROPROCESSOR DESIGN

[David B. <dav...@ya...>]

To All, Has anyone executed a microprocessor design within MyHDL?   Thanks, David Blubaugh


      

Re: [myhdl-list] [new] design flow question

[Neal B. <ndb...@gm...>]

Felton Christopher wrote:

> On the website there are many examples, check out some of the
> following links.
> 
> http://www.myhdl.org/doku.php/publications  -- This is your one stop
> shop, the paper by Dillon Engineering (a bunch of active MyHDL
> contributors) describes exactly what you are looking for
> (http://www.myhdl.org/doku.php/publications ).
> 
> Different examples that have been contributed to the site
> http://www.myhdl.org/doku.php/cookbook:sinecomp   -- Implementation of
> the cordic
> http://www.myhdl.org/doku.php/cookbook:bitonic   	-- Sort algorithm
> implementation
> http://www.myhdl.org/doku.php/projects:cordic_calculations	-- Another
> cordic
> http://www.myhdl.org/doku.php/projects:gcicexample	-- CIC Filter
> http://www.myhdl.org/doku.php/projects:conste_encoder  --
> Constellation Encoder
> 
> Good luck
> 
I'm still a bit lost.  My question is, suppose, for example,  I want to do a design targetting Xylinx.  Suppose I want to use an FIR filter, using Xylinx FIR core generator.  Would this work with a myhdl frontend, and if so, how would the design flow go?

Re: [myhdl-list] [new] design flow question

[Felton C. <chr...@gm...>]

>>
> I'm still a bit lost.  My question is, suppose, for example,  I want  
> to do a design targetting Xylinx.  Suppose I want to use an FIR  
> filter, using Xylinx FIR core generator.  Would this work with a  
> myhdl frontend, and if so, how would the design flow go?
>

What tool do you currently use for your DSP algorithm simulation?

Re: [myhdl-list] [new] design flow question

[Jan D. <ja...@ja...>]

Neal Becker wrote:
>
>>
> I'm still a bit lost.  My question is, suppose, for example,  I want to do a design targetting Xylinx.  Suppose I want to use an FIR filter, using Xylinx FIR core generator.  
> Would this work with a myhdl frontend, and if so, how would the design flow go?

MyHDL is "front-end" in a HDL-based design flow, as an alternative
to Verilog or VHDL. In the ideal case, your HDL designs are
technology-independent, which means that they contain no references
to primitives of specific target technologies. Targetting to
a specific technology is decoupled from this and is accomplished
by a synthesis tool.

The big advantage of HDL-based design like that, is that you are
not tied to a specific vendor, technology or device.

This ideal can be approached very closely, but for obvious
reasons it's not necessarily in an FPGA vendors interest
to tell you this or promote it. Consequently, one obverves
a great deal of difference in "technology independence"
between various design teams. If you want it, you have to
plan for it and keep the discipline.

I have never used any Xilinx core generator, but I assume
that its output is in terms of Xilinx primitives. If so,
this is not compatible with true HDL-based design as outlined
above.

An HDL-based solution could be as follows. Write a fully
parametrized core generator e.g. for a FIR filter in
MyHDL. (It's ideal for such work, seems easy.) Generate
your coefficients using a filter design package, fill
them in, resimulate in MyHDL, convert to Verilog/VHDL.

The output would be technology independent Verilog or
VHDL code for that filter, that you can then target
to anything using a synthesis tool: Xilinx, Altera,
Actel, ASIC implementation ...

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html

Re: [myhdl-list] [new] design flow question

[Newell J. <pil...@gm...>]

I wanted to ask some questions that are similar to the ones that Neal
asked.  I am new to HDL design in general but love programming in Python.
However, I think I will be using a bunch of the open source cores that are
on OpenCores.org.

I would love to start using MyHDL on a regular basis but as of now I don't
really see how I can use MyHDL with all the OpenCores that I would be using
(I am new so if the answer is obvious than excuse me for my ignorance...I am
still learning).
It would really be nice if there was a way to wrap these cores for use in
MyHDL so that in the end I could have a Top Level MyHDL implementation with
embedded cores from OpenCores.

Any ideas if this is possible?

-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] [new] design flow question

[Günter D. <dan...@we...>]

Newell Jensen wrote:
...
> It would really be nice if there was a way to wrap these cores for use in
> MyHDL so that in the end I could have a Top Level MyHDL implementation with
> embedded cores from OpenCores.
> 
> Any ideas if this is possible?
> 

Have a look at this enhancement proposal:

  http://myhdl.org/doku.php/meps:mep-101

Which is implemented now and documented here:

  http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code


Sometimes subjects were already discussed on this mailing list and can
be searched here:

  http://sourceforge.net/mailarchive/forum.php?forum_name=myhdl-list


Hope this helps.

Cheers,

Guenter

Re: [myhdl-list] [new] design flow question

[Jan D. <ja...@ja...>]

Newell Jensen wrote:
> I wanted to ask some questions that are similar to the ones that Neal 
> asked.  I am new to HDL design in general but love programming in 
> Python.  However, I think I will be using a bunch of the open source 
> cores that are on OpenCores.org.
> 
> I would love to start using MyHDL on a regular basis but as of now I 
> don't really see how I can use MyHDL with all the OpenCores that I would 
> be using (I am new so if the answer is obvious than excuse me for my 
> ignorance...I am still learning).
> It would really be nice if there was a way to wrap these cores for use 
> in MyHDL so that in the end I could have a Top Level MyHDL 
> implementation with embedded cores from OpenCores.
> 
> Any ideas if this is possible?

The trick is to include an instantiation of the core using user-defined
code hooks. As Gunter suggests, you should find sufficient documentation
on this.

I'd just like to add a methodology note. It is always desirable to do
simulation, not just using MyHDL as a convertor. Simulation will find
problems that the convertor won't (and can't).

Unfortunately, this means you still need a MyHDL model for such a core.
However, note that when you use a user-defined code hook, the convertor
stops converting at that point. So you can write a model at the highest
level possible using all tricks in the Python book without being
concerned about convertibility.

I recently used this technique to write a simple high-level
behavioral model for a memory structure with a very complicated
Verilog model.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org

Re: [myhdl-list] [new] design flow question

[Newell J. <pil...@gm...>]

On Tue, Dec 23, 2008 at 2:53 AM, Jan Decaluwe <ja...@ja...> wrote:

> Newell Jensen wrote:
> > I wanted to ask some questions that are similar to the ones that Neal
> > asked.  I am new to HDL design in general but love programming in
> > Python.  However, I think I will be using a bunch of the open source
> > cores that are on OpenCores.org.
> >
> > I would love to start using MyHDL on a regular basis but as of now I
> > don't really see how I can use MyHDL with all the OpenCores that I would
> > be using (I am new so if the answer is obvious than excuse me for my
> > ignorance...I am still learning).
> > It would really be nice if there was a way to wrap these cores for use
> > in MyHDL so that in the end I could have a Top Level MyHDL
> > implementation with embedded cores from OpenCores.
> >
> > Any ideas if this is possible?
>
> The trick is to include an instantiation of the core using user-defined
> code hooks. As Gunter suggests, you should find sufficient documentation
> on this.
>
> I'd just like to add a methodology note. It is always desirable to do
> simulation, not just using MyHDL as a convertor. Simulation will find
> problems that the convertor won't (and can't).
>
> Unfortunately, this means you still need a MyHDL model for such a core.
> However, note that when you use a user-defined code hook, the convertor
> stops converting at that point. So you can write a model at the highest
> level possible using all tricks in the Python book without being
> concerned about convertibility.
>

Some of the cores that I am using from OpenCores.org are a CPU....which I
would have no idea on how to do this.  I wish I did, but I am still new to
all this for the most part.


>
> I recently used this technique to write a simple high-level
> behavioral model for a memory structure with a very complicated
> Verilog model.


Yeah, unfortunately I am not as keen on myhdl as you are (I mean, you wrote
it and all).  If I could do this for the CPU, bus, UART, and the Verilog
Wishbone wrapper that I need to make for my DDR2 SDRAM (Xilinx Core
Generator generated) I would be set.

However, I don't see that happening unless I knew what to do etc. and
unfortunately I don't.

Thanks for all the suggestions to everyone though.


>
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      From Python to silicon:
>     http://www.myhdl.org
>
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] [new] design flow question

[Jan D. <ja...@ja...>]

Newell Jensen wrote:

>     I recently used this technique to write a simple high-level
>     behavioral model for a memory structure with a very complicated
>     Verilog model.
> 
> Yeah, unfortunately I am not as keen on myhdl as you are (I mean, you 
> wrote it and all).  If I could do this for the CPU, bus, UART, and the 
> Verilog Wishbone wrapper that I need to make for my DDR2 SDRAM (Xilinx 
> Core Generator generated) I would be set.
> 
> However, I don't see that happening unless I knew what to do etc. and 
> unfortunately I don't.

At least I saved you some frustration up-front :-) No matter how keen I
may be on myhdl, it's more important to be honest and avoid frustration.
Using MyHDL without simulation will get you into trouble. To simulate,
you need models. At this point, MyHDL doesn't have a library like
opencores. It's that simple.

I suggest you use Verilog to tie things together and simulate at the
top level.

If you still want to experiment with MyHDL, do it bottom-up for some
module that you may have design and verify separately. After conversion,
you can then include into the Verilog top-level.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org

[myhdl-list] [patch] convertion of Conditional Expressions in python2.5 and up

[Jian L. <jia...@go...>]

Hi Jan,

I've made a patch for conversion of  Conditional Expressions, e.g:
    x = true_value if condition else false_value
which is new in python 2.5 (not quite new as 3.0 is out :) )

This kind of expressions are widely used in both verilog and vhdl.
I think it's worth to convert it as well, so I made the patch.(see 
attachment)

And don't worry about the python2.4. Conditional expression will not
pass the syntax check in python 2.4 before it fails. So there is no lose 
at all.

btw. Thanks and good job!  MyHDL is so sexy, that I plan to use it in my 
next
project to write a synthesizable cpu.

Best

Jian

[myhdl-list] convertion of Conditional Expressions in python2.5 and up

[Jian L. <jia...@go...>]

Hi Jan,

I've made a patch for conversion of  Conditional Expressions, e.g:
     x = true_value if condition else false_value
which is new in python 2.5 (not quite new as 3.0 is out :) )

This kind of expressions are widely used in both verilog and vhdl.
I think it's worth to convert it as well, so I made the patch.(see
attachment)

And don't worry about the python2.4. Conditional expression will not
pass the syntax check in python 2.4 before it fails. So there is no lose
at all.

btw. Thanks and good job!  MyHDL is so sexy, that I plan to use it in my
next
project to write a synthesizable cpu.

Best

Jian

Re: [myhdl-list] convertion of Conditional Expressions in python2.5 and up

[Jan D. <ja...@ja...>]

Jian LUO wrote:
> Hi Jan,
> 
> I've made a patch for conversion of  Conditional Expressions, e.g:
>     x = true_value if condition else false_value
> which is new in python 2.5 (not quite new as 3.0 is out :) )
> 
> This kind of expressions are widely used in both verilog and vhdl.
> I think it's worth to convert it as well, so I made the patch.(see
> attachment)
> 
> And don't worry about the python2.4. Conditional expression will not
> pass the syntax check in python 2.4 before it fails. So there is no lose
> at all.

Thanks, good to see that someone can make sense of the conversion
source code :-)

I'm going to push this to MyHDL 0.7. There are a few other syntactic sugar
features that will be added in that version, and Python 2.5 can be
made a requirement. Also, a unit test has to be added.

In the future, may I suggest to use mercurial to make patches? The
whole process is described here:

     http://www.myhdl.org/doku.php/dev:patches

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org

Re: [myhdl-list] [new] design flow question

[Neal B. <ndb...@gm...>]

Felton Christopher wrote:

>>>
>> I'm still a bit lost.  My question is, suppose, for example,  I want
>> to do a design targetting Xylinx.  Suppose I want to use an FIR
>> filter, using Xylinx FIR core generator.  Would this work with a
>> myhdl frontend, and if so, how would the design flow go?
>>
> 
> What tool do you currently use for your DSP algorithm simulation?
> 
>
You mean high-level simulation?  I use python with a library of my own based on boost::python and boost::ublas. 

Re: [myhdl-list] [new] design flow question

[David B. <dav...@ya...>]

Neal,  
 
Are you willing to share this library with the rest of us??
 
David Blubaugh 

--- On Sat, 12/20/08, Neal Becker <ndb...@gm...> wrote:

From: Neal Becker <ndb...@gm...>
Subject: Re: [myhdl-list] [new] design flow question
To: myh...@li...
Date: Saturday, December 20, 2008, 5:27 PM

Felton Christopher wrote:

>>>
>> I'm still a bit lost.  My question is, suppose, for example,  I
want
>> to do a design targetting Xylinx.  Suppose I want to use an FIR
>> filter, using Xylinx FIR core generator.  Would this work with a
>> myhdl frontend, and if so, how would the design flow go?
>>
> 
> What tool do you currently use for your DSP algorithm simulation?
> 
>
You mean high-level simulation?  I use python with a library of my own based on
boost::python and boost::ublas. 


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Re: [myhdl-list] [new] design flow question

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> I know only a little about Verilog - I do algorithm development and hand off to coworkers who produce verilog.
> 
> We typically do a lot of DSP work (lots of arithmetic).  Often, things like Xylinx cores are used.
> 
> Would that sort of design flow work with a myhdl frontend?  Any hints?

Sure. This seems to be exactly the case recently highlighted by Chris,
and just added to the advocacy page:

http://www.myhdl.org/doku.php/why#you_would_like_to_do_algorithm_development_and_implementation_in_the_same_environment

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html