Günter Dannoritzer wrote:
> Hi,
>
> With the new intbv.signed() function in the hg repository I tried to
> implement a complex multiplier. To make it a bit more complicated than
> necessary there is only one port for each input operand and one port for
> the output. For each port the upper half of the bits are used for the
> real part of the complex value and the lower half of the bits are for
> the imaginary part.
>
> The simulation of the multiplier works just fine, however, when I
> convert it, the output is set to 0.
>
> This is the MyHDL code I am using to create the output:
>
> @always_comb
> def add_sub_logic():
> y_o.next = concat( intbv(ac - bd)[WIDTH+1:], intbv(bc + ad)[WIDTH+1:] )
>
> and it gets converted to this Verilog code:
>
> assign y_o = {5'h0, 5'h0};
>
>
> Attached is the full code for multiplier and unittest. The conversion
> code is part of cplxMult.py and will be initiated if the file is executed.
>
> Am I doing something basic wrong that I get this result?
No, it's a bug both in VHDL and Verilog. The issue is that slicing an intbv
is typically used to "declare" it and the convertor didn't make the difference
with a cast of an expression.
I have now added a test that checks whether the intbv argument is a constant
or not, to have an appropriate conversion. I have pushed this to the
repository.
I see that the expression is now "preserved" by the convertor, but I have not
yet written a unit test that verifies correctness. A unit test would be welcome :-)
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
From Python to silicon:
http://www.myhdl.org
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