Is there an easy way to get something like a verilog `include into the code
generated by myhdl ? I'm trying to use/synthesize some vendor-supplied code, and
need the generated code to include/reference their primitives.
Thanks!
From: Günter D. <dan...@we...> - 2008-12-10 16:34:52
Eric Jonas wrote:
> Is there an easy way to get something like a verilog `include into the code
> generated by myhdl ? I'm trying to use/synthesize some vendor-supplied code, and
> need the generated code to include/reference their primitives.
>
Have a look at the user-defined Verilog code section in connection with
the converter:
http://www.myhdl.org/doc/0.5.1/manual/conf-usage-custom.html
With the __verilog__ string you can add user defined Verilog code inside
the myhdl code.
Cheers,
Guenter