myhdl-list

[myhdl-list] a few questions relating to recursive designs

[Geoffrey B. <geo...@gm...>]

I thought I'd plunge in with a recursive structure (an N-way mux) which
follows.  I'm embarrassed
how long it took me to figure this out.   Now here are a few questions.

1)  I wanted to use a selector both as a bit vector and an integer.
Naturally
   I made a signal from an intbv, but found the hard way that the obvious
   thing, picking off bits by slicing, doesn't give you what is needed (in
this
   context) -- another signal which has a subset of the bits from the
original

   I resorted to the (ugly) approach of passing an integer through the
hierarchy
   so I could do the bit selection at the leaves.  Another ugly solution
would
   be to define the selector as a list of signals and slice this up.  The
problem
   with this approach is that at the top level of the design one has to
bridge
   from the single intbv to list of signals.

   Any thoughts on a more elegant approach ?

2) It appears that to work with lists of signals, one must ensure that at
the
    instance level the list has been unpacked into individual signals and at
   the top level these lists are built from individual signals.    Is this
correct ?

Geoffrey

--------------------------------------------------

def Mux0(sw, z, A0, A1, sel):
   """ Generate A Two-way Multiplexor

       sw     -- sel bit to use at this level (...,3,2,1,0)
       z      -- data output
       A1, A0 -- data inputs
       sel    -- (multibit) selector
   """
   @always_comb
   def muxLogic():
       if sel[sw]:
           z.next = A1
       else:
           z.next = A0
   return muxLogic


def Mux(sw, z, A, sel):
    """ Recursively Generate A Multiplexor Tree

        sw -- sel bit to use at this level (...,3,2,1,0)
              should match tree depth at top level
         z -- output data
         A -- array of input data
        sel-- selector for array
    """
    assert len(A) >= 2
    if len(A) == 2:
       return Mux0(sw, z, A[0], A[1], sel)
    else:

       # signals for two halves

        Mid  = [Signal(intbv(0)[len(z):]) for i in range(2)]

        # recursively generate muxes for two data halves

        l = len(A)/2
        m1   = Mux(sw-1, Mid[1], A[l:], sel) # top
        m0   = Mux(sw-1, Mid[0], A[:l], sel) # bottom

        # generate top level mux

        top  = Mux(sw, z, Mid, sel)
        return m0, m1, top

Re: [myhdl-list] a few questions relating to recursive designs

[Felton C. <chr...@gm...>]

On May 13, 2009, at 3:31 PM, Geoffrey Brown wrote:

> I thought I'd plunge in with a recursive structure (an N-way mux)  
> which follows.  I'm embarrassed
> how long it took me to figure this out.   Now here are a few  
> questions.
>
> 1)  I wanted to use a selector both as a bit vector and an integer.   
> Naturally
>    I made a signal from an intbv, but found the hard way that the  
> obvious
>    thing, picking off bits by slicing, doesn't give you what is  
> needed (in this
>    context) -- another signal which has a subset of the bits from  
> the original
>
>    I resorted to the (ugly) approach of passing an integer through  
> the hierarchy
>    so I could do the bit selection at the leaves.  Another ugly  
> solution would
>    be to define the selector as a list of signals and slice this  
> up.  The problem
>    with this approach is that at the top level of the design one has  
> to bridge
>    from the single intbv to list of signals.
>
>    Any thoughts on a more elegant approach ?
>
> 2) It appears that to work with lists of signals, one must ensure  
> that at the
>     instance level the list has been unpacked into individual  
> signals and at
>    the top level these lists are built from individual signals.     
> Is this correct ?
>

Well I was going to suggest a list of signals was your best option,  
see the MyHDL below.  But there is a problem with this  
implementation.  The converters want to treat the list of signals (at  
least in this case) as memory.  It assumes that the input, A, is  
internal and not a port.

I still think a list of signals is your best option.   Personally I  
would like to see the list of signals be more generic, not always  
resulting in a memory conversion (see earlier posts).  But the issue  
is how to distinguish a memory model from a generic usage??  In this  
example a little too much freedom (IMO) was taken in the conversion,  
because port A was removed in the resulting Verilog.

If your example was to experiment with the recursive property and not  
simply a mux, I think you can experiment with 'A' and 'sel' being a  
list of signals.

from myhdl import *

def nmux(z, A, sel):
     """
     A    --  List of Signal
     z    --  select output, z type should be the same as the
              types in A
     sel  --  select the signal
     """

     @always_comb
     def muxlogic():
         z.next = A[int(sel)]

     return muxlogic


if __name__ == '__main__':

     N    = 23
     # Direct indexing example
     A    = [Signal(intbv(0)[1:]) for i in range(N)]
     sel  = Signal(intbv(0)[N:])
     z    = Signal(intbv(0)[1:])

     toVerilog(nmux, z, A, sel)

Re: [myhdl-list] a few questions relating to recursive designs

[Felton C. <chr...@gm...>]

>
> 2) It appears that to work with lists of signals, one must ensure  
> that at the
>     instance level the list has been unpacked into individual  
> signals and at
>    the top level these lists are built from individual signals.     
> Is this correct ?
>

Here would be a possible approach, using the list of signals using  
your recursive approach.  There is an issue with it but I thought I  
would share my variant in any case, ran out of time to spend on it.

Re: [myhdl-list] a few questions relating to recursive designs

[Jan D. <ja...@ja...>]

Geoffrey Brown wrote:
> I thought I'd plunge in with a recursive structure (an N-way mux) which 
> follows.  I'm embarrassed
> how long it took me to figure this out.   Now here are a few questions.
> 
> 1)  I wanted to use a selector both as a bit vector and an integer.  
> Naturally
>    I made a signal from an intbv, but found the hard way that the obvious
>    thing, picking off bits by slicing, doesn't give you what is needed 
> (in this
>    context) -- another signal which has a subset of the bits from the 
> original
> 
>    I resorted to the (ugly) approach of passing an integer through the 
> hierarchy
>    so I could do the bit selection at the leaves.  Another ugly solution 
> would
>    be to define the selector as a list of signals and slice this up.  
> The problem
>    with this approach is that at the top level of the design one has to 
> bridge
>    from the single intbv to list of signals.

As other examples illustrate, recursive designs work quite well if you can
use lists of signals.
You can also use intbv Signals in recursion, but then you have to create
intermediate signals and the logic that drives them explicitly. So it
can be done, but this solution would indeed be rather ugly.

Your examples touch the area of MyHDL that I'm least satisfied with:
sometimes there is a valid need to consider the slice/index of a
signal as a signal itself. Currently, this can't be done and it
would require some new ideas/concepts in MyHDL. I would like to
see a breakthrough here and I have some ideas, but that is a
vast subject for separate thread.

>    Any thoughts on a more elegant approach ?
> 
> 2) It appears that to work with lists of signals, one must ensure that 
> at the
>     instance level the list has been unpacked into individual signals and at
>    the top level these lists are built from individual signals.    Is 
> this correct ?

First, any restrictions are related to convertibility, not modeling.

At the very top level, there is the problem that it's unclear how to
map lists of signals to Verilog ports. But again, this is only at the
top level of a design. In other words, it is possible that some module
cannot be converted as a top level design, but is perfectly convertible
within a hierarchy.

I'm not exactly sure what you mean with the restriction at the instance level.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] a few questions relating to recursive designs

[Jan D. <ja...@ja...>]

Geoffrey Brown wrote:
> I thought I'd plunge in with a recursive structure (an N-way mux) which 
> follows.  I'm embarrassed
> how long it took me to figure this out.   Now here are a few questions.
> 
> 1)  I wanted to use a selector both as a bit vector and an integer.  
> Naturally
>    I made a signal from an intbv, but found the hard way that the obvious
>    thing, picking off bits by slicing, doesn't give you what is needed 
> (in this
>    context) -- another signal which has a subset of the bits from the 
> original
> 

Geoffrey:

Please check whether a _SliceSignal would solve your problem:

http://www.myhdl.org/doku.php/meps:mep-105

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] a few questions relating to recursive designs

[Geoffrey B. <geo...@gm...>]

I haven't downloaded the development snapshot, but I'm pretty certain
that what you have designed will work -- either bottom up by concatenating
signals or top down by splitting signals.

In my heart, I wish the extra syntax wasn't needed; however, I take your
point about the efficiency of compiled vs interpreted simulation with
respect
to compound signals.

In any case, I appreciate the effort you've taken in reaction to
the demands of your user community

Geoffrey

On Tue, Jun 23, 2009 at 4:51 AM, Jan Decaluwe <ja...@ja...> wrote:

> Geoffrey Brown wrote:
> > I thought I'd plunge in with a recursive structure (an N-way mux) which
> > follows.  I'm embarrassed
> > how long it took me to figure this out.   Now here are a few questions.
> >
> > 1)  I wanted to use a selector both as a bit vector and an integer.
> > Naturally
> >    I made a signal from an intbv, but found the hard way that the obvious
> >    thing, picking off bits by slicing, doesn't give you what is needed
> > (in this
> >    context) -- another signal which has a subset of the bits from the
> > original
> >
>
> Geoffrey:
>
> Please check whether a _SliceSignal would solve your problem:
>
> http://www.myhdl.org/doku.php/meps:mep-105
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
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