Thread: [myhdl-list] verilog conversion bug ?

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The following is an attempt to create a simple PWM module.   When I simulate
in myhdl and simulate the generated verilog in quartus,
I get different results.  Specifically the "pulse" output is delayed one
clock period in quartus which suggests that my use of
count.next in myhdl doesn't translate into semantically equivalent verilog.
Clearly, I can rewrite things to get the behavior
I want, but I'm worried about the inconsistency.

from myhdl import *

def pwm(clk, clken, width, cycles, pulse):

    count = Signal(intbv(0,cycles.min,cycles.max))

    @always(clk.posedge)
    def pwmlogic():
        if (clken):
            if (count == cycles):
                count.next = 0
            else:
                count.next = count + 1
            if (count.next < width):
                pulse.next = 1
            else:
                pulse.next = 0

    return pwmlogic

if __name__ == '__main__':

    from random import randrange
    clk     = Signal(bool(0))
    clken   = Signal(bool(0))
    width   = Signal(intbv(8)[4:])
    cycles  = Signal(intbv(12)[4:])
    pulse   = Signal(bool(0))

    def test():
        cnt = 0
        for i in range(1000):
            yield delay(10)
            clk.next = not clk
            if (clk):
                if (cnt == 15):
                    clken.next = 1
                    cnt = 0
                else:
                    clken.next = 0
                    cnt = cnt + 1
    pwmbody = traceSignals(pwm, clk, clken, width, cycles, pulse)
    test1 = test()
    sim = Simulation(pwmbody, test1)
    sim.run(quiet=1)

    toVerilog(pwm, clk, clken, width, cycles, pulse)