myhdl-list

[myhdl-list] hierarchy flattening on conversion to vhdl/verilog

[Geoffrey B. <geo...@gm...>]

I'm curious about the decision to elaborate  designs before generation
of vhdl/verilog.  The loss of hierarchy seems unnecessary and makes it
harder to relate the output and input.   What was the thought process
leading to this decision ?

Geoffrey

Re: [myhdl-list] hierarchy flattening on conversion to vhdl/verilog

[Jan D. <ja...@ja...>]

Geoffrey Brown wrote:
> I'm curious about the decision to elaborate  designs before generation
> of vhdl/verilog.  The loss of hierarchy seems unnecessary and makes it
> harder to relate the output and input.   What was the thought process
> leading to this decision ?

About time to turn this into a FAQ :-)

Conversion after elaboration was the insight I needed to make
conversion a feasible project for me. The python interpreter
does as much work as possible and adds information
without which I don't think it is even possible.

Moreover, a nice side effect is that elaboration give you a free
ride on some aspects, for example the conversion restrictions
only apply to code inside generators. Outside them, you can
do what you want which makes some powerful applications.

Look at this (extreme) example:

http://www.myhdl.org/doku.php/cookbook:bitonic

With conversion after elaboration, it is straightforward.
Without it, the recursion would have to be mapped to
Verilog - I'm pretty sure this isn't even possible.

Jan

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Re: [myhdl-list] hierarchy flattening on conversion to vhdl/verilog

[Christopher F. <chr...@gm...>]

>
> The loss of hierarchy seems unnecessary and makes it
> > harder to relate the output and input.
>

If this is desired for debug I imagine it is straight forward enough to have
a script to individually convert each "block".  You would have to manually
wire the top-level.  But it is an option.  For final generation I haven't
notice the flat hierarchy being an issue.


> Conversion after elaboration was the insight I needed to make
> conversion a feasible project for me. The python interpreter
> does as much work as possible and adds information
> without which I don't think it is even possible.


In my opinion this is one of the huge benefits of MyHDL (Python based HDL)
over the traditional HDLs.  There is a lot of power in this feature.