myhdl-list

[myhdl-list] Wraparound addition?

[Andrew L. <bs...@al...>]

How do I add two unsigned intbv() objects such that the addition wraps 
around?

Obviously, I can do the addition and then mask it and reassign like so:

new = (old0 + old1) & 0xffff

However, I doubt that is going to translate to verilog properly.

-a

Re: [myhdl-list] Wraparound addition?

[Günter D. <dan...@we...>]

Andrew Lentvorski wrote:
> How do I add two unsigned intbv() objects such that the addition wraps 
> around?
> 
> Obviously, I can do the addition and then mask it and reassign like so:
> 
> new = (old0 + old1) & 0xffff
> 
> However, I doubt that is going to translate to verilog properly.

There had been a discussion about that feature back in June of last year 
  on this mailing list. Here is a link to the achieve of that:

http://sourceforge.net/mailarchive/forum.php?forum_name=myhdl-list&max_rows=25&style=ultimate&viewmonth=200706

Jan had written some background information about the intention of intbv 
there in connection with the wrap around functionality.

This might be a good question to be answered on the FAQ page.

Cheers,

Guenter

Re: [myhdl-list] Wraparound addition?

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:
> Andrew Lentvorski wrote:
>> How do I add two unsigned intbv() objects such that the addition wraps 
>> around?
>>
>> Obviously, I can do the addition and then mask it and reassign like so:
>>
>> new = (old0 + old1) & 0xffff
>>
>> However, I doubt that is going to translate to verilog properly.
> 
> There had been a discussion about that feature back in June of last year 
>   on this mailing list. Here is a link to the achieve of that:
> 
> http://sourceforge.net/mailarchive/forum.php?forum_name=myhdl-list&max_rows=25&style=ultimate&viewmonth=200706
> 
> Jan had written some background information about the intention of intbv 
> there in connection with the wrap around functionality.
> 
> This might be a good question to be answered on the FAQ page.

Ok, what about this:

http://myhdl.jandecaluwe.com/doku.php/faq#how_do_i_describe_wrap-around_behaviour


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Wraparound addition?

[Christopher L. F. <cf...@uc...>]

>>>
>>
>> There had been a discussion about that feature back in June of last  
>> year
>>  on this mailing list. Here is a link to the achieve of that:
>>
>> http://sourceforge.net/mailarchive/forum.php?forum_name=myhdl-list&max_rows=25&style=ultimate&viewmonth=200706
>>
>> Jan had written some background information about the intention of  
>> intbv
>> there in connection with the wrap around functionality.
>>
>> This might be a good question to be answered on the FAQ page.
>
> Ok, what about this:
>
> http://myhdl.jandecaluwe.com/doku.php/faq#how_do_i_describe_wrap-around_behaviour
>



Ok more on the wrap functionality.  I know this has come up a couple  
times and may have been answered.  The page referenced above has an  
example for an unsigned counter.  In the case for signed values I  
don't think the mod works?

As previously discussed the 2's complement wrap is often exploited in  
DSP.  The solution thus far has been to design within limits (no  
wrapping).  There are some scenarios that the resources required tends  
to using the 2's comp wrap.  Below is an example that illustrates the  
mod function to support the wrap in MyHDL.  I am missing how this can  
be applied to a signed value and still be convertible.  I haven't been  
able to think of any elegant solutions other than handling a bunch of  
different cases to handle negatives.

Increment Wrap Start Zero
    0     1     2     3     4     5     6     7     0     1     2      
3     4     5     6
    7     0     1     2     3     4     5     6     7     0     1      
2     3     4     5
    6     7     0     1     2     3     4     5     6     7     0      
1     2     3     4
    5     6     7     0     1     2     3     4     5     6     7      
0     1     2     3
    4     5     6     7     0     1     2     3     4     5     6      
7     0     1     2
    3     4     5     6     7     0     1     2     3     4     5     6

Decrement Wrap Start Positive
    7     6     5     4     3     2     1     0     7     6     5      
4     3     2     1
    0     7     6     5     4     3     2     1     0     7     6      
5     4     3     2
    1     0     7     6     5     4     3     2     1     0     7      
6     5     4     3
    2     1     0     7     6     5     4     3     2     1     0      
7     6     5     4
    3     2     1     0     7     6     5     4     3     2     1      
0     7     6     5
    4     3     2     1     0     7     6     5     4     3     2     1

Increment Wrap Start Negative -8
   -8     1     2     3     4     5     6     7     0     1     2      
3     4     5     6
    7     0     1     2     3     4     5     6     7     0     1      
2     3     4     5
    6     7     0     1     2     3     4     5     6     7     0      
1     2     3     4
    5     6     7     0     1     2     3     4     5     6     7      
0     1     2     3
    4     5     6     7     0     1     2     3     4     5     6      
7     0     1     2
    3     4     5     6     7     0     1     2     3     4     5     6

Decrement Wrap Start Negative -1
   -1     6     5     4     3     2     1     0     7     6     5      
4     3     2     1
    0     7     6     5     4     3     2     1     0     7     6      
5     4     3     2
    1     0     7     6     5     4     3     2     1     0     7      
6     5     4     3
    2     1     0     7     6     5     4     3     2     1     0      
7     6     5     4
    3     2     1     0     7     6     5     4     3     2     1      
0     7     6     5
    4     3     2     1     0     7     6     5     4     3     2     1


from myhdl import *

Q = 3
L = 2**Q
x = intbv(0, min=-L, max=L)

print '\n\nIncrement Wrap Start Zero'
for i in range(1, 11*L):
     print '%4d ' % x,
     x[:] = (x + 1) % L

     if i%15 == 0:
         print ''

print '\n\nDecrement Wrap Start Positive'
for i in range(1, 11*L):
     print '%4d ' % x,
     x[:] = (x - 1) % L

     if i%15 == 0:
         print ''

print '\n\nIncrement Wrap Start Negative -%d' % L
x[:] = -L
for i in range(1, 11*L):
     print '%4d ' % x,
     x[:] = (x + 1) % L

     if i%15 == 0:
         print ''

print '\n\nDecrement Wrap Start Negative -1'
x[:] = -1
for i in range(1, 11*L):
     print '%4d ' % x,
     x[:] = (x - 1) % L

     if i%15 == 0:
         print ''

Re: [myhdl-list] Wraparound addition?

[Thomas T. <tho...@de...>]

Andrew Lentvorski wrote:
> How do I add two unsigned intbv() objects such that the addition wraps 
> around?
> 
> Obviously, I can do the addition and then mask it and reassign like so:
> 
> new = (old0 + old1) & 0xffff

> However, I doubt that is going to translate to verilog properly.


The following short test code can be used to try the mask approach and
the modulo approach (suggested by Jan some weeks ago).

BTW: Some german websites say that the Verilog arithmetic is defined as
wrap around arithmetic. Therefore the implementation of the wrapping
behaviour I suggested last year and again some weeks ago, is a quite
simple simulator code modification only.

--------------------------------------
from myhdl import *


def wrap(inp,out):

    @always_comb
    def w():
        #out.next = (inp +1) & 0xffff
        out.next = (inp +1)%2**16
    return instances()

i = Signal(intbv(0)[16:])
o = Signal(intbv(0)[16:])

toVerilog(wrap,i,o)
-----------------------------------------

The results (not tested):
-----------------------------------------
// File: wrap.v
// Generated by MyHDL 0.6dev8
// Date: Mon Aug 11 09:13:15 2008

`timescale 1ns/10ps

module wrap (
    inp,
    out
);

input [15:0] inp;
output [15:0] out;
wire [15:0] out;

assign out = ((inp + 1) & 65535);

endmodule
-----------------------------------------
/ File: wrap.v
// Generated by MyHDL 0.6dev8
// Date: Mon Aug 11 09:10:13 2008

`timescale 1ns/10ps

module wrap (
    inp,
    out
);

input [15:0] inp;
output [15:0] out;
wire [15:0] out;

assign out = ((inp + 1) % (2 ** 16));

endmodule
-----------------------------------------