Thread: [myhdl-list] myhdl with cython?
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From: David B. <da...@be...> - 2016-01-26 08:43:03
|
Dear All, i've been fiddling with myhdl for about a week or so. I've tried to do some real stuff I do at work using myhdl. As a part of the project involves FIR filtering, I have used the example found on Christopher Felton's page (https://bitbucket.org/cfelton/examples) and hacked away m_firfilt entity using my own coefficients. Now, my filter has 891 taps and I've tried to simulate using a testbench how it reacts on unit-amplitude (it is a bandpass) input signal. It works great, at the same time it takes 'ages'. Simulation of such filter with roughly 5000 clock cycles takes almost 2 minutes. 4 times longer than I do with modelsim (from mentor). So I wanted to check, whether it is feasible to use cython for these things. Following http://docs.cython.org/src/tutorial/cython_tutorial.html I hae created the setup and compiled in-the module using build_ext --inplace. All that works OK, but then I tried to import the compiled module in python, and I get: -------------------------------------------------------------------------------- >>> import FIR_tb Working Loaded 891 coefficients Traceback (most recent call last): File "<stdin>", line 1, in <module> File "FIR_tb.pyx", line 46, in init FIR_tb (FIR_tb.c:2580) tbm = traceSignals(tb) File "/usr/local/lib/python2.7/dist-packages/myhdl-1.0dev-py2.7.egg/myhdl/_traceSignals.py", line 85, in __call__ h = _HierExtr(name, dut, *args, **kwargs) File "/usr/local/lib/python2.7/dist-packages/myhdl-1.0dev-py2.7.egg/myhdl/_extractHierarchy.py", line 238, in __init__ _top = dut(*args, **kwargs) File "FIR_tb.pyx", line 19, in FIR_tb.tb (FIR_tb.c:1720) @always(delay(10)) File "/usr/local/lib/python2.7/dist-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py", line 54, in _always_decorator raise AlwaysError(_error.ArgType) myhdl.AlwaysError: decorated object should be a classic (non-generator) function -------------------------------------------------------------------------------- for a testbench, which works OK when ran as a python module (non-compiled). For the sake of completeness here is the testbench (the entity itself is the same as in Christopher's examples) -------------------------------------------------------------------------------- from myhdl import * from FIR import * print "Working" def tb(): # read FIR coeffs coeffs = map(int, open("/home/belohrad/git/didt/Python/firfilter/filter_coefficients_newline.txt", "rt").readlines()) print "Loaded ", len(coeffs), " coefficients" DxD, QxD = [Signal(intbv(0)[32:0].signed()) for x in xrange(2)] ResetxRN = ResetSignal(0, active = 0, async=True) ClkxC = Signal(bool(0)) i_fir = m_firfilt (ClkxC, ResetxRN, DxD, QxD, coeffs) @always(delay(10)) def driveClk(): ClkxC.next = not ClkxC @instance def tbi(): ResetxRN.next = 0 DxD.next = 0 yield(delay(150)) yield (ClkxC.posedge) ResetxRN.next = 1 yield (ClkxC.posedge) # test unity but this is a band-pass filter for i in xrange(4906): DxD.next = 1 yield (ClkxC.posedge) DxD.next = 0 yield (ClkxC.posedge) DxD.next = -1 yield (ClkxC.posedge) DxD.next = 0 yield (ClkxC.posedge) raise StopSimulation() return tbi, driveClk, i_fir tbm = traceSignals(tb) sim = Simulation(tbm).run() print "Done" -------------------------------------------------------------------------------- Now, the error message is very cryptic to me. Is there anyone who tried to use cython for simulation? Is this error fatal and I cannot use cython at all due to some technical restrictions? Thanks .david. |
From: Jan C. <jen...@mu...> - 2016-01-26 13:12:52
|
On Tue, 26 Jan 2016 09:13:16 +0100 David Belohrad <da...@be...> wrote: > It works great, at the same time it takes 'ages'. Simulation > of such filter with roughly 5000 clock cycles takes almost 2 > minutes. 4 times longer than I do with modelsim (from mentor). > > So I wanted to check, whether it is feasible to use cython for > these things. Following > http://docs.cython.org/src/tutorial/cython_tutorial.html I hae > created the setup and compiled in-the module using build_ext Might this help a little: http://www.myhdl.org/docs/performance.html Jan Coombs |
From: Christopher F. <chr...@gm...> - 2016-01-26 13:13:40
|
On 1/26/2016 2:13 AM, David Belohrad wrote: > i've been fiddling with myhdl for about a week or so. I've tried to > do some real stuff I do at work using myhdl. As a part of the project > involves FIR filtering, I have used the example found on Christopher > Felton's page (https://bitbucket.org/cfelton/examples) and hacked > away m_firfilt entity using my own coefficients. Now, my filter has > 891 taps and I've tried to simulate using a testbench how it reacts > on unit-amplitude (it is a bandpass) input signal. > > It works great, at the same time it takes 'ages'. Simulation of such > filter with roughly 5000 clock cycles takes almost 2 minutes. 4 times > longer than I do with modelsim (from mentor). If you haven't seen this page it has some useful information: http://www.myhdl.org/docs/performance.html > > So I wanted to check, whether it is feasible to use cython for these > things. Following > http://docs.cython.org/src/tutorial/cython_tutorial.html I hae > created the setup and compiled in-the module using build_ext > --inplace. > I have not tried cython but I won't be surprised that it would fail. It seems reasonable that you could maybe compile only the function As far as the error posted, it seems the cython changed the function somehow but that is just a guess. Regards, Chris |
From: David B. <da...@be...> - 2016-01-26 14:05:08
|
Ok, It seems that I have missed that page. I'll check with PyPy then. Thanks .d. Christopher Felton <chr...@gm...> writes: > On 1/26/2016 2:13 AM, David Belohrad wrote: >> i've been fiddling with myhdl for about a week or so. I've tried to >> do some real stuff I do at work using myhdl. As a part of the project >> involves FIR filtering, I have used the example found on Christopher >> Felton's page (https://bitbucket.org/cfelton/examples) and hacked >> away m_firfilt entity using my own coefficients. Now, my filter has >> 891 taps and I've tried to simulate using a testbench how it reacts >> on unit-amplitude (it is a bandpass) input signal. >> >> It works great, at the same time it takes 'ages'. Simulation of such >> filter with roughly 5000 clock cycles takes almost 2 minutes. 4 times >> longer than I do with modelsim (from mentor). > > If you haven't seen this page it has some useful information: > http://www.myhdl.org/docs/performance.html > > >> >> So I wanted to check, whether it is feasible to use cython for these >> things. Following >> http://docs.cython.org/src/tutorial/cython_tutorial.html I hae >> created the setup and compiled in-the module using build_ext >> --inplace. >> > > I have not tried cython but I won't be surprised that > it would fail. It seems reasonable that you could > maybe compile only the function > > As far as the error posted, it seems the cython changed > the function somehow but that is just a guess. > > Regards, > Chris > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: David B. <da...@be...> - 2016-01-26 14:55:41
|
Just checked and it seems that it improves performance by roughly 8 times! That is indeed massive and I think I'm around the times I get with modelsim. belohrad@beesknees:~/git/didt/MyHDL/FIR$ time pypy ./FIR_tb.py Working Loaded 891 coefficients Done real 0m19.081s user 0m16.208s sys 0m0.640s belohrad@beesknees:~/git/didt/MyHDL/FIR$ time python ./FIR_tb.py Working Loaded 891 coefficients Done real 2m21.629s user 2m17.020s sys 0m1.476s belohrad@beesknees:~/git/didt/MyHDL/FIR$ .d. Christopher Felton <chr...@gm...> writes: > On 1/26/2016 2:13 AM, David Belohrad wrote: >> i've been fiddling with myhdl for about a week or so. I've tried to >> do some real stuff I do at work using myhdl. As a part of the project >> involves FIR filtering, I have used the example found on Christopher >> Felton's page (https://bitbucket.org/cfelton/examples) and hacked >> away m_firfilt entity using my own coefficients. Now, my filter has >> 891 taps and I've tried to simulate using a testbench how it reacts >> on unit-amplitude (it is a bandpass) input signal. >> >> It works great, at the same time it takes 'ages'. Simulation of such >> filter with roughly 5000 clock cycles takes almost 2 minutes. 4 times >> longer than I do with modelsim (from mentor). > > If you haven't seen this page it has some useful information: > http://www.myhdl.org/docs/performance.html > > >> >> So I wanted to check, whether it is feasible to use cython for these >> things. Following >> http://docs.cython.org/src/tutorial/cython_tutorial.html I hae >> created the setup and compiled in-the module using build_ext >> --inplace. >> > > I have not tried cython but I won't be surprised that > it would fail. It seems reasonable that you could > maybe compile only the function > > As far as the error posted, it seems the cython changed > the function somehow but that is just a guess. > > Regards, > Chris > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Christopher F. <chr...@gm...> - 2016-01-26 15:00:20
|
On 1/26/2016 8:51 AM, David Belohrad wrote: > Just checked > > and it seems that it improves performance by roughly 8 times! That is > indeed massive and I think I'm around the times I get with modelsim. > Which version of pypy did you use? Regards, Chris |
From: David B. <da...@be...> - 2016-01-26 15:43:55
|
belohrad@beesknees:~/git/didt/MyHDL/FIR$ pypy --version Python 2.7.8 (2.4.0+dfsg-3, Dec 20 2014, 13:30:46) [PyPy 2.4.0 with GCC 4.9.2] debian (testing?) Christopher Felton <chr...@gm...> writes: > On 1/26/2016 8:51 AM, David Belohrad wrote: >> Just checked >> >> and it seems that it improves performance by roughly 8 times! That is >> indeed massive and I think I'm around the times I get with modelsim. >> > > Which version of pypy did you use? > > Regards, > Chris > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Edward V. <dev...@sb...> - 2016-01-26 21:51:34
|
Hello All,I was reading David's post and found it very interesting. I tested on a RPi2B and did not get the results that David posted. At first, I thought the Pillow was taking all of time. My question, what would taking all of time? These are the steps that I used. Testing pypy on RPi2B jessie >From the site below http://pypy.org/download.html Python2.7 compatible PyPy 4.0.1 https://bitbucket.org/pypy/pypy/downloads/pypy-4.0.1-linux-armhf-raspbian.tar.bz2 wget https://bitbucket.org/pypy/pypy/downloads/pypy-4.0.1-linux-armhf-raspbian.tar.bz2 bzip2 -d pypy-4.0.1-linux-armhf-raspbian.tar.bz2 cd /opt/ sudo tar xvf /home/pi/pypy-4.0.1-linux-armhf-raspbian.tar Needed to install myhdl in pypy cd ~/myhdl/ sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy setup.py install Needed to install pip in pypy wget https://bootstrap.pypa.io/get-pip.py sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy get-pip.py Needed to install Pillow in pypy sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy -m pip install Pillow ls /opt/pypy-4.0.1-linux-armhf-raspbian/site-packages/ easy_install.py _markerlib myhdl-1.0dev-py2.7.egg-info Pillow-3.1.0.dist-info pip-8.0.2.dist-info README setuptools-19.6.dist-info wheel-0.26.0.dist-info easy_install.pyc myhdl PIL pip pkg_resources setuptools wheel Testing the times to run with python & pypy time python test_top.py --test real 0m8.363s user 0m8.210s sys 0m0.080s time /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy test_top.py --test real 0m40.811s user 0m38.620s sys 0m0.480s I created a version that did not use the Image libtime python nopil_test_top.py --test real 0m7.943s user 0m7.790s sys 0m0.140s time /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy nopil_test_top.py --test real 0m26.320s user 0m26.060s sys 0m0.220s As before the pypy took longer than the python one. It appears that the Image reading only took less than .5 sec. Did I fail to do something?https://github.com/develone/jpeg-2000-test/tree/master/pc_fast_blinker_jpeg Do you not get the benefit, until you exceed the time, to convert the python to compiled? Initially I was only testing a few values. To do the complete image the test bench will grow very quickly. Regards, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Tuesday, January 26, 2016 8:44 AM, David Belohrad <da...@be...> wrote: belohrad@beesknees:~/git/didt/MyHDL/FIR$ pypy --version Python 2.7.8 (2.4.0+dfsg-3, Dec 20 2014, 13:30:46) [PyPy 2.4.0 with GCC 4.9.2] debian (testing?) Christopher Felton <chr...@gm...> writes: > On 1/26/2016 8:51 AM, David Belohrad wrote: >> Just checked >> >> and it seems that it improves performance by roughly 8 times! That is >> indeed massive and I think I'm around the times I get with modelsim. >> > > Which version of pypy did you use? > > Regards, > Chris > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Edward V. <dev...@sb...> - 2016-01-27 16:01:59
|
Hello All, When you convert to Verilog, I see that `timescale 1ns/10ps near the top of the file .I don't see any timing information when you convert to VHDL. On the CAT-Board the default clock is 100MHz & on XulA2-LX9 the default clock is 12MHz.With the DCM I convert to 120MHz. For my simulation my clock is always 20nsec or 50MHz. Why? Can someone explain? @always(delay(10)) def clkgen(): clock.next = not clock If my simulation takes 1m35.611s using pypy, but total simulation time is 9139190 ns. What is the FPGA time? What is taking most of time? Modified to send more values to simulation. Now pypy is 2.3 times faster than python. pi@mysshserver ~/jpeg-2000-test/pc_fast_blinker_jpeg $ time python test_top.py --test real 3m38.582s user 3m36.950s sys 0m0.630s pi@mysshserver ~/jpeg-2000-test/pc_fast_blinker_jpeg $ rm -f tb.vcd*pi@mysshserver ~/jpeg-2000-test/pc_fast_blinker_jpeg $ time /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy test_top.py --test real 1m35.611s user 1m34.780s sys 0m0.800s Thanks, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Tuesday, January 26, 2016 2:51 PM, Edward Vidal <dev...@sb...> wrote: Hello All,I was reading David's post and found it very interesting. I tested on a RPi2B and did not get the results that David posted. At first, I thought the Pillow was taking all of time. My question, what would taking all of time? These are the steps that I used. Testing pypy on RPi2B jessie >From the site below http://pypy.org/download.html Python2.7 compatible PyPy 4.0.1 https://bitbucket.org/pypy/pypy/downloads/pypy-4.0.1-linux-armhf-raspbian.tar.bz2 wget https://bitbucket.org/pypy/pypy/downloads/pypy-4.0.1-linux-armhf-raspbian.tar.bz2 bzip2 -d pypy-4.0.1-linux-armhf-raspbian.tar.bz2 cd /opt/ sudo tar xvf /home/pi/pypy-4.0.1-linux-armhf-raspbian.tar Needed to install myhdl in pypy cd ~/myhdl/ sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy setup.py install Needed to install pip in pypy wget https://bootstrap.pypa.io/get-pip.py sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy get-pip.py Needed to install Pillow in pypy sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy -m pip install Pillow ls /opt/pypy-4.0.1-linux-armhf-raspbian/site-packages/ easy_install.py _markerlib myhdl-1.0dev-py2.7.egg-info Pillow-3.1.0.dist-info pip-8.0.2.dist-info README setuptools-19.6.dist-info wheel-0.26.0.dist-info easy_install.pyc myhdl PIL pip pkg_resources setuptools wheel Testing the times to run with python & pypy time python test_top.py --test real 0m8.363s user 0m8.210s sys 0m0.080s time /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy test_top.py --test real 0m40.811s user 0m38.620s sys 0m0.480s I created a version that did not use the Image libtime python nopil_test_top.py --test real 0m7.943s user 0m7.790s sys 0m0.140s time /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy nopil_test_top.py --test real 0m26.320s user 0m26.060s sys 0m0.220s As before the pypy took longer than the python one. It appears that the Image reading only took less than .5 sec. Did I fail to do something?https://github.com/develone/jpeg-2000-test/tree/master/pc_fast_blinker_jpeg Do you not get the benefit, until you exceed the time, to convert the python to compiled? Initially I was only testing a few values. To do the complete image the test bench will grow very quickly. Regards, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Tuesday, January 26, 2016 8:44 AM, David Belohrad <da...@be...> wrote: belohrad@beesknees:~/git/didt/MyHDL/FIR$ pypy --version Python 2.7.8 (2.4.0+dfsg-3, Dec 20 2014, 13:30:46) [PyPy 2.4.0 with GCC 4.9.2] debian (testing?) Christopher Felton <chr...@gm...> writes: > On 1/26/2016 8:51 AM, David Belohrad wrote: >> Just checked >> >> and it seems that it improves performance by roughly 8 times! That is >> indeed massive and I think I'm around the times I get with modelsim. >> > > Which version of pypy did you use? > > Regards, > Chris > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Christopher F. <chr...@gm...> - 2016-01-27 18:27:46
|
On 1/27/2016 10:01 AM, Edward Vidal wrote: > Hello All, When you convert to Verilog, I see that `timescale > 1ns/10ps near the top of the file .I don't see any timing information > when you convert to VHDL. On the CAT-Board the default clock is > 100MHz & on XulA2-LX9 the default clock is 12MHz.With the DCM I > convert to 120MHz. For my simulation my clock is always 20nsec or > 50MHz. Why? Can someone explain? @always(delay(10)) def clkgen(): > clock.next = not clock If my simulation takes 1m35.611s using pypy, > but total simulation time is 9139190 ns. What is the FPGA time? The MyHDL simulator does not specify an absolute physical time unit for each simulation time-step. It's yours to determine (e.g. `delay(1)` can be 1ns if you like). It gets a little more complicated when creating VCD files and converting. When "tracing" the VCD file and the V* time literals need to know the units. For tracing the time unit embedded in the VCD file and is controlled by the `traceSignals.timescale` attribute and the default is "1ns". In [2]: traceSignals.timescale Out[2]: '1ns' If you are using the defaults and in your waveform viewer you see 9,139,160 ns your real-time will be 9.1ms and your clock will be the 50MHz as viewed in the waveform viewer. If I change `traceSignals.timescale = '1ps' and nothing else in my test code. The clock will be 50GHz and the simulated time will be 9.1us as observed in the waveform viewer Hope that helps, Chris |
From: Edward V. <dev...@sb...> - 2016-01-29 23:58:53
|
Hi All,Yes Chris, what you provided helped quite a bit. I have continued to add more work to the simulation and have tested on both the a 6 core AMD with Ubuntu 12.04 and the RPi2B with RaspBian Jessie. The results are below. On a 6-Core AMD runningUbuntu 12.04 the simulation takes vidal@ws009:~/wkg/jpeg-2000-test/pc_fast_blinker_jpeg$time python test_top_a.py --testreal 1m6.287suser 1m6.036ssys 0m0.228s On a RPi2B with pypy thesimulation takes time/opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy test_top_a.py --testreal 4m22.736suser 4m17.710ssys 0m2.180s pi@mysshserver~/jpeg-2000-test/pc_fast_blinker_jpeg $ time python test_top_a.py--testreal 12m31.381suser 12m19.160ssys 0m2.330sUsing pypy provides a 1.43times improvement over python. Simulation time in GTKWave. 23,039,990 ns 23.03 msec at50MHzIs this what I could expect on a XulA2-LX9 running at 120MHz or CAT-Board at 100MHz. | 120000000 | 2.4 | 9.60E-003 | | 100000000 | 2 | 1.15E-002 | My simulation is "python test_top_a.py --test" https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/test_top_a.py In the document https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/multi_instance_simulation.pdf In Appendix B I have python code that I need to convert to HDL, since it is currently used twice in the simulation.What is the best method to do this conversion? Would like to use 16 instances instead of 4 which I am currently using. Thanks in advance.Regards, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Wednesday, January 27, 2016 11:28 AM, Christopher Felton <chr...@gm...> wrote: On 1/27/2016 10:01 AM, Edward Vidal wrote: > Hello All, When you convert to Verilog, I see that `timescale > 1ns/10ps near the top of the file .I don't see any timing information > when you convert to VHDL. On the CAT-Board the default clock is > 100MHz & on XulA2-LX9 the default clock is 12MHz.With the DCM I > convert to 120MHz. For my simulation my clock is always 20nsec or > 50MHz. Why? Can someone explain? @always(delay(10)) def clkgen(): > clock.next = not clock If my simulation takes 1m35.611s using pypy, > but total simulation time is 9139190 ns. What is the FPGA time? The MyHDL simulator does not specify an absolute physical time unit for each simulation time-step. It's yours to determine (e.g. `delay(1)` can be 1ns if you like). It gets a little more complicated when creating VCD files and converting. When "tracing" the VCD file and the V* time literals need to know the units. For tracing the time unit embedded in the VCD file and is controlled by the `traceSignals.timescale` attribute and the default is "1ns". In [2]: traceSignals.timescale Out[2]: '1ns' If you are using the defaults and in your waveform viewer you see 9,139,160 ns your real-time will be 9.1ms and your clock will be the 50MHz as viewed in the waveform viewer. If I change `traceSignals.timescale = '1ps' and nothing else in my test code. The clock will be 50GHz and the simulated time will be 9.1us as observed in the waveform viewer Hope that helps, Chris ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Christopher F. <chr...@gm...> - 2016-01-27 17:57:49
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> My question, what would taking all of time? The pypy jit has a "warm-up" time it will not improve run-time on simulations that execute quickly (less than a minute?). Regards, Chris |
From: David B. <da...@be...> - 2016-01-28 08:06:44
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when talking about pypy - has anyone succeeded to install there scipy? I'm using that quite a lot to do all the signal analysis. I did not manage to install it so for the moment I have to stick to cPython to do myhdl (as from such analyses I usually get bit widths and coefficients and other funny stuff). .d. Christopher Felton <chr...@gm...> writes: > > My question, what would taking all of time? > > The pypy jit has a "warm-up" time it will not improve > run-time on simulations that execute quickly (less > than a minute?). > > Regards, > Chris > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Christopher F. <chr...@gm...> - 2016-01-28 13:07:35
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On 1/28/2016 2:02 AM, David Belohrad wrote: > when talking about pypy - has anyone succeeded to install there > scipy? I'm using that quite a lot to do all the signal analysis. I > did not manage to install it so for the moment I have to stick to > cPython to do myhdl (as from such analyses I usually get bit widths > and coefficients and other funny stuff). > > .d. No, I have not successfully used numpy/scipy with pypy. In the past I have done one of the following: 1) ran the HDL simulation separate in pypy and analysis in cpython; 2) implemented the functions I needed in pure python [1]. There seem to be some pure numpy implementations that can be used with pypy: https://github.com/wadetb/tinynumpy https://bitbucket.org/dblank/pure-numpy Regards, Chris [1] https://speakerdeck.com/cfelton/python-scientific-and-numerical-computing-fast-with-pypy > > > > Christopher Felton <chr...@gm...> writes: > >>> My question, what would taking all of time? >> >> The pypy jit has a "warm-up" time it will not improve run-time on >> simulations that execute quickly (less than a minute?). >> >> Regards, Chris >> >> |