myhdl-list

[myhdl-list] choice of free Verilog simulator: icarus vs cver

[George P. <ge...@ga...>]

Hi Jan,

   Did cver overthrow icarus Verilog for the title of Officially
Sanctioned Verilog Simlator now? How much does the choice matter?

Thanks,
--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] choice of free Verilog simulator: icarus vs cver

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi Jan,
> 
>    Did cver overthrow icarus Verilog for the title of Officially
> Sanctioned Verilog Simlator now?

No - I've had issues with both and want to use both for increased
confidence (in the MyHDL convertor).

> How much does the choice matter?

Depends on what you're doing with which version :-)

When I introduced support for 'signed' in the Verilog conversion,
I inevitably ended up in some of the darkest corners of the
Verilog language. Not unexpectedly, the simulators behaved
differently and it turned out that Icarus (0.8) had bugs.

To be sure, I filed bug reports, they were acknowledged, and
have been reported to be fixed by now. At that time I continued
with cver to make progress.

Cver may seem more robust, but has its issues also. E.g. the
'RandomScrambler' test takes ages with cver (unacceptably long),
but not with Icarus.

Probably it's time for me to upgrade my installations. But
since I'm doing VHDL these days ... (GHDL seems to work
very well, by the way.)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] choice of free Verilog simulator: icarus vs cver

[George P. <ge...@ga...>]

> George Pantazopoulos wrote:
>> Hi Jan,
>>
>>    Did cver overthrow icarus Verilog for the title of Officially
>> Sanctioned Verilog Simlator now?
>
> No - I've had issues with both and want to use both for increased
> confidence (in the MyHDL convertor).
>
>> How much does the choice matter?
>
> Depends on what you're doing with which version :-)
>
> To be sure, I filed bug reports, they were acknowledged, and
> have been reported to be fixed by now. At that time I continued
> with cver to make progress.
>

Oh, I may want to stick with Icarus, then, as long as the signed
arithmetic stuff is fixed. Is it ok to use the latest snapshot? If not,
can you recommend a particular one?

>
> Probably it's time for me to upgrade my installations. But
> since I'm doing VHDL these days ... (GHDL seems to work
> very well, by the way.)
>

Yeah, I've been curious as to what you've been up to, since you seem
pretty busy ;-) How is the VHDL and tristate support going?

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] choice of free Verilog simulator: icarus vs cver

[<dan...@we...>]

George Pantazopoulos wrote:
> 
> Oh, I may want to stick with Icarus, then, as long as the signed
> arithmetic stuff is fixed. Is it ok to use the latest snapshot? If not,
> can you recommend a particular one?
> 

Hi George,

I recently installed the latest snapshot 20060809 under cygwin and had
to do some adjusting to get it to compile.

First there is a bug report:

http://sourceforge.net/tracker/index.php?func=detail&aid=1541452&group_id=149850&atid=775997

with a patch file:

http://sourceforge.net/tracker/download.php?group_id=149850&atid=775997&file_id=194444&aid=1541452

>From all what is said in that bug report the patch file is the one to
apply to the source.


Then there is another change that has to be done:

> Stephen Williams wrote:
> [...]
>> > 
>> > Try adding ivl_lval_width to the ivl.def file in the main source
>> > directory, then rebuild from the top down. It looks like that got
>> > missed in the big fixup.

That did it for me.

Guenter

Re: [myhdl-list] choice of free Verilog simulator: icarus vs cver

[George P. <ge...@ga...>]

> That did it for me.
>
>   

That worked for me too. Thanks a LOT!

George