myhdl-list

Re: [myhdl-list] Re: co-simulation: vpi file

[George P. <ge...@ga...>]

Please disregard the other message with no subject line. My apologies.


> I reviewed the toVerilog tests with Icarus. I have 2
> groups of failures:
>
> - test_bugreports fails because of the missing verilogCompile
> - test_inc has a failing test because of a bug in the test suite
>
> I have solved these issues in my development code.
>
> - test_dec has failing tests because of Icarus bugs with signed
> - test_signed has failing tests because of Icarus bugs with signed
>
>
> If you see the same, you can ignore the failures for now and it
> basically means that you got it to work on Windows. That is
> good news - thanks for the efforts.

Hi Jan,

   I added the definition of verilogCompileIcarus to util.py and set
"verilogCompile =3D verilogCompileIcarus" and re-ran test_all.py in
myhdl/test/toVerilog. Now almost all the test pass, except for the ones
you mentioned (I've pasted just the four error messages below. So I guess
this means myHDL 0.5a1 and Icarus 0.8.2 do work on WindowsXP with cygwin
:)

Would you recommend that I transistion to cver? Which has the more active
development and community?

Also, I got my own myHDL/cosim unit tests to pass by inserting yield
delay(10) statements between a signal changing and the time I do a
assertEqual() on it. Also, adding delay(10) to the very beginning of each
test function seemed to help some cases. It seems like somewhat of a
kludge, though. Is that the right thing to do? What are the guidelines fo=
r
this sort of thing? You did mention not to compare at time 0. Did you mea=
n
time 0 from the start of the entire simulation? Or did you mean time 0
from the start of each signal changing?

Thanks,
George

errors from test_all.py:

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
ERROR: testDecFunc (test_dec.TestDec)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/tmp/myhdl-0.5a1/myhdl/test/toVerilog/test_dec.py", line 196, in
testDecFunc
    sim =3D self.bench(decFunc)
  File "/tmp/myhdl-0.5a1/myhdl/test/toVerilog/test_dec.py", line 179, in
bench
    dec_inst_v =3D dec_v(dec.func_name, count_v, enable, clock, reset)
  File "/tmp/myhdl-0.5a1/myhdl/test/toVerilog/test_dec.py", line 126, in
dec_v
    return setupCosimulation(**locals())
  File "/tmp/myhdl-0.5a1/myhdl/test/toVerilog/util.py", line 15, in
setupCosimulationIcarus
    return Cosimulation(simulate_cmd, **kwargs)
  File "/usr/lib/python2.4/site-packages/myhdl/_Cosimulation.py", line
91, in __init__
    raise CosimulationError(_error.SimulationEnd)
CosimulationError: Premature simulation end

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
FAIL: Check increment operation
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/tmp/myhdl-0.5a1/myhdl/test/toVerilog/test_inc.py", line 176, in
testInc2
    sim.run(quiet=3D1)
  File "/usr/lib/python2.4/site-packages/myhdl/_Simulation.py", line
132, in run
    waiter.next(waiters, actives, exc)
  File "/usr/lib/python2.4/site-packages/myhdl/_Waiter.py", line 70, in n=
ext
    clause =3D self.generator.next()
  File "/tmp/myhdl-0.5a1/myhdl/test/toVerilog/test_inc.py", line 140, in
check
    self.assertEqual(count, count_v)
AssertionError: Signal(intbv(1L)) !=3D Signal(intbv(0L))

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
FAIL: testAugmOps (test_signed.TestAugmOps)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/tmp/myhdl-0.5a1/myhdl/test/toVerilog/test_signed.py", line 482,
in testAugmOps
    Simulation(sim).run()
  File "/usr/lib/python2.4/site-packages/myhdl/_Simulation.py", line
132, in run
    waiter.next(waiters, actives, exc)
  File "/usr/lib/python2.4/site-packages/myhdl/_Waiter.py", line 70, in n=
ext
    clause =3D self.generator.next()
  File "/tmp/myhdl-0.5a1/myhdl/test/toVerilog/test_signed.py", line 465,
in check
    self.assertEqual(Mul, Mul_v)
AssertionError: Signal(intbv(4056L)) !=3D Signal(intbv(-9256))

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
FAIL: testBinaryOps (test_signed.TestBinaryOps)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/tmp/myhdl-0.5a1/myhdl/test/toVerilog/test_signed.py", line 236,
in testBinaryOps
    Simulation(sim).run()
  File "/usr/lib/python2.4/site-packages/myhdl/_Simulation.py", line
132, in run
    waiter.next(waiters, actives, exc)
  File "/usr/lib/python2.4/site-packages/myhdl/_Waiter.py", line 70, in n=
ext
    clause =3D self.generator.next()
  File "/tmp/myhdl-0.5a1/myhdl/test/toVerilog/test_signed.py", line 207,
in check
    self.assertEqual(Mul, Mul_v)
AssertionError: Signal(intbv(-9700)) !=3D Signal(intbv(55836))

---------------------------------------------------------------------- Ra=
n
129 tests in 251.108s

FAILED (failures=3D3, errors=3D1)



--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Re: co-simulation: vpi file

[<dan...@we...>]

George Pantazopoulos wrote:

> 
> Would you recommend that I transistion to cver? Which has the more active
> development and community?
> 

I was able to install cver under cygwin just fine, however, when trying
to run the PLI examples, ran into some problems. It basically has to do
that you have to run a certain (older) version of cygwin in order to get
it going.

On this page:

http://www.pragmatic-c.com/gpl-cver/windows.htm

I found this link to a file, that has the details about it:

 	"To use the PLI on Cygwin please read the README in 	
	tests_and_examples/examples.vpi."

> Also, I got my own myHDL/cosim unit tests to pass by inserting yield
> delay(10) statements between a signal changing and the time I do a
> assertEqual() on it. Also, adding delay(10) to the very beginning of each
> test function seemed to help some cases. It seems like somewhat of a
> kludge, though. Is that the right thing to do? What are the guidelines for
> this sort of thing? You did mention not to compare at time 0. Did you mean
> time 0 from the start of the entire simulation? Or did you mean time 0
> from the start of each signal changing?

I ran into that too. Actually a delay(1) is already sufficient.

I believe this has to do with the nature of simulating a flip-flop
behavior and you will find that in every HDL simulator.

Consider the following statement in HDL simulation.


	yield clk.posedge

	a.next = input
	b.next = a

In software programming a and b would have the same value. In HDL b will
get the result of a one clock cycle later. In the simulation the
decision is made at the positive edge of the clock. Consider this as the
point when time stands still in the simulator. Now the simulator needs
to make a decision about the assignments. For the assignments it takes
the values it last knew, which is one timestep before the positive edge.
It does the assignments and turns time on again. Now you are one
timestep after the positive edge and the values would be available for
assignment. As you want to look at the values, this is the time you want
to be at to get the correct values.

I hope I explained that correct. Anyone please correct me if I am wrong.

There is actually a book, I found good in explaining writing
testbenches, co-simulation, etc. It also talks about different types of
simulators.

Writing Testbenches, 2nd edition
by Janick Bergeron
Kluwer Academic Publishers


Cheers,

Guenter