myhdl-list

[myhdl-list] toVerilog does not like the logging module

[<dan...@we...>]

Hi,

I started using the logging module of python to print out debugging 
information instead of just using print functions. The nice feature 
about this is that the logging information can be left in the code and 
just disabled by setting the level to what level should print out 
accordingly.

However, it seems like toVerilog does not like logging entries, as it 
canceled on them with an Assertion Error. This is maybe not only a 
logging problem as there are many other python modules that could be 
included in code. Off course there is the question how much sense it 
makes to include modules in a part of code that is meant for being 
translated by toVerilog anyway.

I was just wondering whether it would be beneficial to have some type of 
ignore function that allows to specify modules that should be ignored by 
toVerilog? So for example if I do a:

	import logging


I can do

	myhdl.ignore(logging)


and toVerilog will ignore any statements of the type:

	logging.debug(...)


Regards,

Guenter

Re: [myhdl-list] toVerilog does not like the logging module

[Jan D. <ja...@ja...>]

--- Günter Dannoritzer <dan...@we...> wrote:

> Hi,
> 
> I started using the logging module of python to
> print out debugging 
> information instead of just using print functions.
> The nice feature 
> about this is that the logging information can be
> left in the code and 
> just disabled by setting the level to what level
> should print out 
> accordingly.
> 
> However, it seems like toVerilog does not like
> logging entries, as it 
> canceled on them with an Assertion Error. This is
> maybe not only a 
> logging problem as there are many other python
> modules that could be 
> included in code. Off course there is the question
> how much sense it 
> makes to include modules in a part of code that is
> meant for being 
> translated by toVerilog anyway.

Currently, what you can do is include code to be
ignored in an if __debug__ statement.

This was included in 0.4.1 but the manual was not
updated with that release. Browse the RFE section on
SourceForge for (closed) issues.

Jan


> 
> I was just wondering whether it would be beneficial
> to have some type of 
> ignore function that allows to specify modules that
> should be ignored by 
> toVerilog? So for example if I do a:
> 
> 	import logging
> 
> 
> I can do
> 
> 	myhdl.ignore(logging)
> 
> 
> and toVerilog will ignore any statements of the
> type:
> 
> 	logging.debug(...)
> 
> 
> Regards,
> 
> Guenter
> 
> 
> 
>
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