myhdl-list

[myhdl-list] Opencores project

[David B. <dav...@fr...>]

All,

I have posted a project on Opencores. It is a MyHDL model of a turbo deco=
der,
still at an early stage of development. You might want to check it out at=
:
http://www.opencores.org/projects/turbocodes/

Regards,

David.

[myhdl-list] Re: Opencores project

[Jan D. <ja...@ja...>]

David Brochart wrote:
> All,
> 
> I have posted a project on Opencores. It is a MyHDL model of a turbo decoder,
> still at an early stage of development. You might want to check it out at:
> http://www.opencores.org/projects/turbocodes/

Thanks for your efforts - I will definitely check this out further!

I believe that real, relevant projects such as this one are the ideal way
to increase awareness and usefulness of MyHDL. I would encourage everybody
to suggest potential projects, ideally in a "hot" domain with
commercial relevance. At some point I would like to do such a project
myself also.

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium

[myhdl-list] Re: Opencores project

[Guenter D. <dan...@we...>]

David Brochart wrote:

> All,
> 
> I have posted a project on Opencores. It is a MyHDL model of a turbo decoder,
> still at an early stage of development. You might want to check it out at:
> http://www.opencores.org/projects/turbocodes/
> 
> Regards,
> 
> David.
> 

David,

I looked into you project to study MyHDL and recognized that there is
some toVerilog usage, but in the description it does not say anything
that the MyHDL implementation is able to generate Verilog code. Also you
added the VHDL synthesizeable code.

Did you need the code in VHDL or was there some other reason not to use
the toVerilog?

From you experience how well can the toVerilog be used to generate
Verilog code?

I saw in a different thread that it is not possible to generate lists of
Signals. Is there a different way to model Verilog generateable memory?

Thanks for you thoughts.

Guenter

[myhdl-list] Re: Opencores project

[David B. <dav...@fr...>]

Guenter,

If there is some toVerilog usage in the MyHDL description, just forget it=
. It
was a trial and I will clean that in the next release. I realized that I =
was
using much too complex structures in order for toVerilog to translate the=
m
(multi-dimensional arrays, list of instanciations...). I started writing =
a
toVHDL equivalent to toVerilog because I know what I want to be translate=
d and
I'm more familiar in VHDL than in Verilog, but I'm not finished with it a=
nd I
thought that a synthezisable description of the project would be more use=
full,
so that's why I translated it by hand in VHDL. Also, my toVHDL translator=
 was
not so clean and as Jan said, it is important to start with a clean spec =
of the
things that should be translated and the things that should not. So I wil=
l need
to spend more time on the toVHDL translator.
From my experience the current toVerilog cannot be used in a real project=
. But
it can be easily improved by adding more and more features.

Regards,

David.



Selon Guenter Dannoritzer <dan...@we...>:

> David Brochart wrote:
>
> > All,
> >
> > I have posted a project on Opencores. It is a MyHDL model of a turbo
> decoder,
> > still at an early stage of development. You might want to check it ou=
t at:
> > http://www.opencores.org/projects/turbocodes/
> >
> > Regards,
> >
> > David.
> >
>
> David,
>
> I looked into you project to study MyHDL and recognized that there is
> some toVerilog usage, but in the description it does not say anything
> that the MyHDL implementation is able to generate Verilog code. Also yo=
u
> added the VHDL synthesizeable code.
>
> Did you need the code in VHDL or was there some other reason not to use
> the toVerilog?
>
> From you experience how well can the toVerilog be used to generate
> Verilog code?
>
> I saw in a different thread that it is not possible to generate lists o=
f
> Signals. Is there a different way to model Verilog generateable memory?
>
> Thanks for you thoughts.
>
> Guenter
>
>
>
>
>
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Re: [myhdl-list] Re: Opencores project

[<dan...@we...>]

David,

David Brochart wrote:

...

> (multi-dimensional arrays, list of instanciations...). I started writing a
> toVHDL equivalent to toVerilog because I know what I want to be translated and
> I'm more familiar in VHDL than in Verilog, but I'm not finished with it 
...

That is great, so there is a toVHDL in progress.

> Also, my toVHDL translator was
> not so clean and as Jan said, it is important to start with a clean spec of the
> things that should be translated and the things that should not. So I will need
> to spend more time on the toVHDL translator.

Did you start out with the toVerilog? I was reading a bit how the
toVerilog works and I was wondering whether a quick trick would be to
take the part that generates the Verilog code and just replace it by
VHDL. But I guess I am not that experienced with VHDL and Verilog to see
whether that really would go that easy.


>>From my experience the current toVerilog cannot be used in a real project. But
> it can be easily improved by adding more and more features.
> 
> Regards,
> 
> David.
> 

Thanks for sharing that.

Guenter



...

[myhdl-list] Re: Opencores project

[David B. <dav...@fr...>]

G=FCnter,

Yes, I started from the toVerilog for the toVHDL convertor. It is quite e=
asy to
identify where to replace the Verilog generated code with the VHDL genera=
ted
code. But the thing is that MyHDL looks like Verilog in its structure, an=
d VHDL
is quite different, so that is where the difficulty is.

Regards,

David.



Selon G=FCnter Dannoritzer <dan...@we...>:

> David,
>
> David Brochart wrote:
>
> ...
>
> > (multi-dimensional arrays, list of instanciations...). I started writ=
ing a
> > toVHDL equivalent to toVerilog because I know what I want to be trans=
lated
> and
> > I'm more familiar in VHDL than in Verilog, but I'm not finished with =
it
> ...
>
> That is great, so there is a toVHDL in progress.
>
> > Also, my toVHDL translator was
> > not so clean and as Jan said, it is important to start with a clean s=
pec of
> the
> > things that should be translated and the things that should not. So I=
 will
> need
> > to spend more time on the toVHDL translator.
>
> Did you start out with the toVerilog? I was reading a bit how the
> toVerilog works and I was wondering whether a quick trick would be to
> take the part that generates the Verilog code and just replace it by
> VHDL. But I guess I am not that experienced with VHDL and Verilog to se=
e
> whether that really would go that easy.
>
>
> >>From my experience the current toVerilog cannot be used in a real pro=
ject.
> But
> > it can be easily improved by adding more and more features.
> >
> > Regards,
> >
> > David.
> >
>
> Thanks for sharing that.
>
> Guenter
>
>
>
> ...
>
>
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>

[myhdl-list] Re: Opencores project

[Jan D. <ja...@ja...>]

David Brochart wrote:
> Günter,
> 
> Yes, I started from the toVerilog for the toVHDL convertor. It is quite easy to
> identify where to replace the Verilog generated code with the VHDL generated
> code. But the thing is that MyHDL looks like Verilog in its structure, and VHDL
> is quite different, so that is where the difficulty is.

If it looks more like Verilog, that´s certainly not the intention :-)

For crucial features, the main inspiration has been VHDL, for example
the delta-cycle algorithm, the strict separation between signals and
variables, strong typing (thanks to Python of course), ...

However, I certainly believe that writing toVHDL by starting from
toVerilog is difficult. Here are two considerations:

- Verilog is a lower level language, with loose typing. This may
make it easier in the direction from MyHDL to Verilog. Easier,
because they are more different, in this case :-)

- the main reason is probably that toVerilog has code that may
*seem* generic, but isn´t. In the ideal case, there would be a
generic analyzer, with just a dedicated backend in the conversion
stage. However, that´s not the case. The whole thing was certainly
written with Verilog in mind. If I would write toVHDL, I would start
from scratch (benefiting from the toVerilog experience, of course.)

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html

[myhdl-list] Re: Opencores project

[Jan D. <ja...@ja...>]

David Brochart wrote:

> From my experience the current toVerilog cannot be used in a real project. But
> it can be easily improved by adding more and more features.

It could be either expectations that are too high, or a
feature set that is too small. I would like to find that
out, so to avoid any misunderstandings I´ll first describe
my view on the role of toVerilog in a real project.

In a project of certain complexity, it is normal to find 2
levels of modeling:

1. a very high level reference model. This is a model to
experiment with algorithms and architectures, with little
concern for implementation details. MyHDL should be a
good choice here. Others may use C, C++, SystemC, Matlab,
perl ...

2. an implementation-oriented model. Used to synthesize or
define the implementation. Typically done in Verilog or VHDL.

I think this matches what you have done in your project.

The role of toVerilog is not to convert a type 1 model into
a type 2 model. Considering the extreme power of Python
(which is very useful for type 1 modeling) this seems like
an impossible task.

Rather, the purpose of toVerilog is that the type 2 model
can *also* be written in MyHDL, instead of having to use
another language. Potential benefits: familiar language,
partial reuse of code and verification environment, potentially
several backends (Verilog, VHDL) from a single code base.

In short, one would still have to write 2 models, but both could
be in MyHDL. However, learning about the ´´synthesizable subset´´
will still be unavoidable for type 2 modeling.

If we agree on the above, we can consider the feature set.
I have not done any real projects myself with MyHDL or toVerilog,
so I cannot judge wether the feature set is sufficient, although
the intention with the release was that it would be. On the
other hand, I´m pretty sure that I would also encounter difficulties
in a real project.

The suggested approach to improve things is one feature at a time.
Start a discussion on the most pressing feature, with a rationale
and a small example. The more specific, the better.
The current discussion on Verilog memories is a good example.

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html

Re: [myhdl-list] Re: Opencores project

[Tom D. <td...@di...>]

I will add my thoughts to this:

Our designs which are normally math oriented, need a model up front to=20
be sure the implementation will work, just a math model, but it really=20
has to be bit accurate to prove the logic implementation of the =20
algorithm will work in a math sense. It is a good thing if this model=20
can be created very rapidly and makes it easy to explore different=20
alternatives to the implementation.

After that the model needs to be turned into logic and the logic is=20
tested against the model to verify it is implemented properly. I would=20
not expect to be able to synthesize anything like the math model and end=20
up with logic that would be useful. So a logic representation must be=20
created, hopefully using a lot of modules already designed in MyHDL and=20
easily accessible (parametric and tested).

MyHDL has the potential to do this very well, as python is a great place=20
to do the modeling and MyHDL allows for the simulation and conversion to=20
logic along with verification of the converted logic.

Tom





Jan Decaluwe wrote:

> David Brochart wrote:
>
>> From my experience the current toVerilog cannot be used in a real=20
>> project. But
>> it can be easily improved by adding more and more features.
>
>
> It could be either expectations that are too high, or a
> feature set that is too small. I would like to find that
> out, so to avoid any misunderstandings I=B4ll first describe
> my view on the role of toVerilog in a real project.
>
> In a project of certain complexity, it is normal to find 2
> levels of modeling:
>
> 1. a very high level reference model. This is a model to
> experiment with algorithms and architectures, with little
> concern for implementation details. MyHDL should be a
> good choice here. Others may use C, C++, SystemC, Matlab,
> perl ...
>
> 2. an implementation-oriented model. Used to synthesize or
> define the implementation. Typically done in Verilog or VHDL.
>
> I think this matches what you have done in your project.
>
> The role of toVerilog is not to convert a type 1 model into
> a type 2 model. Considering the extreme power of Python
> (which is very useful for type 1 modeling) this seems like
> an impossible task.
>
> Rather, the purpose of toVerilog is that the type 2 model
> can *also* be written in MyHDL, instead of having to use
> another language. Potential benefits: familiar language,
> partial reuse of code and verification environment, potentially
> several backends (Verilog, VHDL) from a single code base.
>
> In short, one would still have to write 2 models, but both could
> be in MyHDL. However, learning about the =B4=B4synthesizable subset=B4=B4
> will still be unavoidable for type 2 modeling.
>
> If we agree on the above, we can consider the feature set.
> I have not done any real projects myself with MyHDL or toVerilog,
> so I cannot judge wether the feature set is sufficient, although
> the intention with the release was that it would be. On the
> other hand, I=B4m pretty sure that I would also encounter difficulties
> in a real project.
>
> The suggested approach to improve things is one feature at a time.
> Start a discussion on the most pressing feature, with a rationale
> and a small example. The more specific, the better.
> The current discussion on Verilog memories is a good example.
>
> Regards, Jan
>

Re: [myhdl-list] Re: Opencores project

[<dan...@we...>]

Jan,

Jan Decaluwe wrote:

...

> In a project of certain complexity, it is normal to find 2
> levels of modeling:
> 
> 1. a very high level reference model. This is a model to
> experiment with algorithms and architectures, with little
> concern for implementation details. MyHDL should be a
> good choice here. Others may use C, C++, SystemC, Matlab,
> perl ...
> 
> 2. an implementation-oriented model. Used to synthesize or
> define the implementation. Typically done in Verilog or VHDL.
> 
> I think this matches what you have done in your project.

...

> In short, one would still have to write 2 models, but both could
> be in MyHDL. However, learning about the ´´synthesizable subset´´
> will still be unavoidable for type 2 modeling.
> 

That approach has the disadvantage that 2 separate models have to be
done. I think MyHDL has the potential to combine that and that would be
a great benefit as it could speed up the development process.

Just as one example, there are numerous math functions available for
python that makes it in some cases a perfect substitute for Matlab.


> If we agree on the above, we can consider the feature set.

I agree on that, but would like to discuss a 3. feature and that is some
kind of framework that allows to merge the 2 features.

...

> 
> The suggested approach to improve things is one feature at a time.
> Start a discussion on the most pressing feature, with a rationale
> and a small example. The more specific, the better.
> The current discussion on Verilog memories is a good example.
> 
> Regards, Jan
> 

I agree, that first two features need to be set in order to add the
third idea. I would like to describe it here, in order to see whether it
is really feasible.

My idea is to have some type of framework class, that is the basic
building block to model with MyHDL. Instead of using functions that
resemble modules in Verilog my suggestion would be to use classes.

To model, one would derive a class from the framework class, which
provides predefined member functions that need to be filled with logic.

One member function is for the *behavioral* modeling and is used to do
the higher layer modeling. Level 1 as you called it.

So it is possible to model just with that, create instances of the class
and run it with the MyHDL simulator as before.


The merge would come from a second member function that allows to do the
*rtl* or level 2 modeling. In that member function it is possible to
model the logic in a way that it can be converted with toVerilog and
create synthesizable logic.

The advantage from that approach would be that behavioral and rtl
modeling are close together, grouped together in an object oriented
manner. That would allow to do verification on the individual class
instances.

One idea would be for example that there is a third member function that
allows to run the simulation of the behavioral model, take data from
that and compare it with co-simulation results of the toVerilog code.

Now I am not that experienced with MyHDL and logic development in
general to know what an effort that proposed framework would be. Also I
am not sure whether classes would become too complex, as it would hold
behavioral, rtl modeling and verification code.

It would be interesting to hear some of your thoughts about this idea.


Regards,

Guenter