myhdl-list

[myhdl-list] toVerilog conversion question

[Newell J. <pil...@gm...>]

All,

I am trying to create a case statement in Verilog that relies on other
Signals such as this:
(THIS WOULD BE THE VERILOG AFTER CONVERSION, where dwb_mx is a Signal that
is 32 bits)

    4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};
    4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};
    4'h2: mem_mx <= #1 {24'd0, dwb_mx[15:8]};
    4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};
    . . .
    . . .
    . . .

Is there a way to do this?  I have been struggling to get my conversion to
something like this and was wondering if it is possible.  All the examples
that I looked at online are case statements that already know the values on
the right side of => .  That is, when the tuple is made with constants.  I
guess I could do a bunch of if statements... but didn't know if there was
another way to do this more elegantly within MyHDL.

Thanks,

-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] toVerilog conversion question

[Brendan R. <bre...@gm...>]

Newell Jensen <pillar2012 <at> gmail.com> writes:

> 
> All,I am trying to create a case statement in Verilog that relies on other
Signals such as this:(THIS WOULD BE THE VERILOG AFTER CONVERSION, where dwb_mx
is a Signal that is 32 bits)    4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};   
4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};    4'h2: mem_mx <= #1 {24'd0,
dwb_mx[15:8]};    4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};
>     . . .    . . .    . . .Is there a way to do this?  I have been struggling
to get my conversion to something like this and was wondering if it is
possible.  All the examples that I looked at online are case statements that
already know the values on the right side of => .  That is, when the tuple is
made with constants.  I guess I could do a bunch of if statements... but didn't
know if there was another way to do this more elegantly within MyHDL.Thanks,--
Newellhttp://www.gempillar.comBefore enlightenment: chop wood, carry waterAfter
enlightenment: code, build circuits

The last I heard, Guido doesn't like case/switch statements.  :-)  If statements
and concat() are what I would use.  The converter will insert case statements
into the Verilog where appropriate.  I used the following LJ article to get
going with this sort of thing:

http://www.linuxjournal.com/article/7542

The CookBook and other resources on myhdl.org are also very useful references.

Cheers,

- Brendan

Re: [myhdl-list] toVerilog conversion question

[Newell J. <pil...@gm...>]

>
>
> The last I heard, Guido doesn't like case/switch statements.  :-)


Thanks...but I am well aware of that.  Maybe you don't understand my
question.


>  If statements
> and concat() are what I would use.  The converter will insert case
> statements
> into the Verilog where appropriate.


Not necessarily.  I understand that if you have an enumeration or a tuple of
hardcoded values then it will work.  However, my question is whether or not
there is a way to update Signals with other Signals (i.e. Signals which
change on the right side of the non-blocking assignment <=).  I have been
having issues doing this and have not found anything in the documentation or
cookbook.

If you point me to a specific example then maybe I will see what you are
trying to say.  Thanks for the effort though.



>  I used the following LJ article to get
> going with this sort of thing:
>
> http://www.linuxjournal.com/article/7542
>
> The CookBook and other resources on myhdl.org are also very useful
> references.
>
> Cheers,
>
> - Brendan
>
>
>
> ------------------------------------------------------------------------------
> This SF.net email is sponsored by:
> SourcForge Community
> SourceForge wants to tell your story.
> http://p.sf.net/sfu/sf-spreadtheword
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] toVerilog conversion question

[Newell J. <pil...@gm...>]

Just to clarify on my last post after re-reading it.  Brendan...when I was
referring to case statements I was referring to the Verilog case statement.
I know that Python does not have case statements.

To keep it simple without getting mixed up in words I am just trying to get
a case statement like the one in my initial posting.  If anyone has clues on
how to get a toVerilog conversion that would be able to spit out....that is
what I am after.

Thanks,

On Fri, Jan 30, 2009 at 10:11 PM, Newell Jensen <pil...@gm...>wrote:

>
>
>>
>> The last I heard, Guido doesn't like case/switch statements.  :-)
>
>
> Thanks...but I am well aware of that.  Maybe you don't understand my
> question.
>
>
>>  If statements
>> and concat() are what I would use.  The converter will insert case
>> statements
>> into the Verilog where appropriate.
>
>
> Not necessarily.  I understand that if you have an enumeration or a tuple
> of hardcoded values then it will work.  However, my question is whether or
> not there is a way to update Signals with other Signals (i.e. Signals which
> change on the right side of the non-blocking assignment <=).  I have been
> having issues doing this and have not found anything in the documentation or
> cookbook.
>
> If you point me to a specific example then maybe I will see what you are
> trying to say.  Thanks for the effort though.
>
>
>
>>  I used the following LJ article to get
>> going with this sort of thing:
>>
>> http://www.linuxjournal.com/article/7542
>>
>> The CookBook and other resources on myhdl.org are also very useful
>> references.
>>
>> Cheers,
>>
>> - Brendan
>>
>>
>>
>> ------------------------------------------------------------------------------
>> This SF.net email is sponsored by:
>> SourcForge Community
>> SourceForge wants to tell your story.
>> http://p.sf.net/sfu/sf-spreadtheword
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
> Newell
>
> http://www.gempillar.com
> Before enlightenment: chop wood, carry water
> After enlightenment: code, build circuits
>



-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] toVerilog conversion question

[Jan D. <ja...@ja...>]

Newell Jensen wrote:
> All,
> 
> I am trying to create a case statement in Verilog that relies on other 
> Signals such as this:
> (THIS WOULD BE THE VERILOG AFTER CONVERSION, where dwb_mx is a Signal 
> that is 32 bits)
> 
>     4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};
>     4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};
>     4'h2: mem_mx <= #1 {24'd0, dwb_mx[15:8]};
>     4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};
>     . . .
>     . . .
>     . . .
> 
> Is there a way to do this?  I have been struggling to get my conversion 
> to something like this and was wondering if it is possible.  All the 
> examples that I looked at online are case statements that already know 
> the values on the right side of => .  That is, when the tuple is made 
> with constants.  I guess I could do a bunch of if statements... but 
> didn't know if there was another way to do this more elegantly within MyHDL.

There are two separate cases when the convertor uses case statements:

1) to implement indexing into a tuple of constant integers
This is not what you're after here.

2) when it detects that the conditions in an if-elsif-esle control
structure are exclusive.
This is what you're after. I'm going to expand on this further.

As Python doesn't have a case statement, the straightforward way is to
map MyHDL if/elsif statements to Verilog if/elsif statements. The only
good reason to use case statements (+ pragmas) instead is because in
that way you can express exclusivity, which may result in a more
efficient implementation.

Currently, the convertor doesn't try to detect exclusivity based on
numbers. I don't think that would be very worthwhile. Instead, MyHDL
supports enumeration types, which let you express exclusive conditions
explicitly, like in VHDL.

When I look at your code, it seems it's trying to express one-hot
encoding. In my opinion, it's clearer and less error-prone to use
an enum type to represent the choices symbolically, and define
(or change!) the desired encoding at a single place in the code.
The enum type constructor has a parameter for this.

The documentation (see link below) is perhaps a little confusing.
It suggest that this optimization is only for FSMs. While that
is an important application, the optimization is actually general.
Whenever a enum type is used to indicate exclusivity in a control
structure, a case statement will be used in Verilog or VHDL.
It doesn't matter what you do inside the control structure.

http://www.myhdl.org/doc/0.6/manual/conversion_examples.html#optimizations-for-finite-state-machines

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org