Thread: [myhdl-list] Cosimulation help

Brought to you by: jandecaluwe

myhdl-list

[myhdl-list] Cosimulation help

From: Newell J. <pil...@gm...> - 2009-04-01 06:15:50

Wondering if anyone might be able to help me with a Cosimulation error that
I am getting.
I am using py.test and don't know if this is the reason I am getting the
error.  Any suggestions
are welcome.

Here is the error:

jensen@ubuntu-2012:~/Desktop/python$ py.test simulate
Traceback (most recent call last):
  File "/usr/bin/py.test", line 10, in <module>
    py.test.cmdline.main()
  File "/usr/lib/python2.5/site-packages/py/test/cmdline.py", line 15, in
main
    failures = session.main()
  File "/usr/lib/python2.5/site-packages/py/test/session.py", line 57, in
main
    colitems = self.config.getcolitems()
  File "/usr/lib/python2.5/site-packages/py/test/config.py", line 65, in
getcolitems
    return [self._getcollector(path) for path in (trails or self.args)]
  File "/usr/lib/python2.5/site-packages/py/test/config.py", line 77, in
_getcollector
    return col._getitembynames(names)
  File "/usr/lib/python2.5/site-packages/py/test/collect.py", line 149, in
_getitembynames
    assert next is not None, (cur, name, namelist)
AssertionError: (<Directory 'python'>, 'simulate', ['simulate'])


And here is the script that I am running (simulate):

#! /usr/bin/env python

import os

from myhdl import *

cmd = "iverilog -o simple_bench -cconffile.txt"
WB_PERIOD = 10

# Make a clk generator for pci_clock, wb_clock
# Make a 32 bit signal for listening to the reg AD

def bench():
    """ Practice Unit Test for the opencores PCI project """

    pci_clock = Signal(bool(0))
    wb_clock = Signal(bool(0))
    AD = Signal(intbv(0, min=0, max=2**32))

    dut = simple_bench(pci_clock, wb_clock, AD)

    @always(delay(10))
    def pci_clkgen():
        pci_clock.next = not pci_clock

    @always(delay(WB_PERIOD/2))
    def wb_clkgen():
        wb_clock.next = not wb_clock

    @always(pci_clock.negedge)
    def monitor():
        print AD

    return pci_clkgen, wb_clkgen, monitor, dut

def test_bench():
    sim = Simulation(bench())
    sim.run()

def simple_bench(pci_clock, wb_clock, AD):
    os.system(cmd)
    return Cosimulation("vvp -m ./myhdl.vpi simple_bench",
pci_clock=pci_clock, wb_clock=wb_clock, AD=AD)


-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

[myhdl-list] intbv return types

From: Christopher L. F. <chr...@gm...> - 2009-04-12 03:31:10

Curiosity, what was the rational behind the mathematical operators for 
the intbv object returning the integer values and the logic operators 
(shifts, and, or, xor, etc) returning an intbv object?

Example
a = intbv(1)
b = intbv(2)

c = a + b
type(c)
<type 'int'>

c = a ^ b
type(c)
<class 'myhdl._intbv.intbv'>

Thanks
Chris

Re: [myhdl-list] intbv return types

From: Jan D. <ja...@ja...> - 2009-04-19 08:08:59

Christopher L. Felton wrote:
> Curiosity, what was the rational behind the mathematical operators for 
> the intbv object returning the integer values and the logic operators 
> (shifts, and, or, xor, etc) returning an intbv object?
> 
> Example
> a = intbv(1)
> b = intbv(2)
> 
> c = a + b
> type(c)
> <type 'int'>
> 
> c = a ^ b
> type(c)
> <class 'myhdl._intbv.intbv'>

If the return value is an intbv, you can slice and index it.
This probably makes sense for "bit-oriented" operations,
and perhaps less for "arithmetic" operations.
Therefore, for the latter case it might be a good idea
to avoid the overhead of intbv construction.

This is all a little bit arbitrary and speculative -
for example, I haven't done tests to check how significant
the intbv construction overhead exactly is.
We always have the option to change the return type
to intbv if there's a real need.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com