> Early 2008 I designed the digital controller in a mixed-signal
> ASIC design with MyHDL.
>
> Overall, the project has been a big success and soon the chip
> will go into high-volume production (millions).
>
> I have now received permission to write a paper about the
> role that MyHDL played in the project. Needless to say, I'm
> very proud on this accomplishment. In a project like this,
> reliability and cost are crucial. Therefore, this will also
> be my answer to those who question the reliability and
> efficiency of MyHDL-based design - an answer in silicon!
>
> I'm aware of several FPGA projects that have been completed
> successfully with MyHDL, but no ASIC projects so far. So
> I'm going to claim this is the first ASIC tape-out, unless
> someone tells me otherwise! (This can be in private email.)
>
> Best regards,
>
> Jan
>
Congratulations!!!! That is a very big milestone for MyHDL and very
exciting. Good job with all the hard work!
Kudos again.
Chris
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