myhdl-list

[myhdl-list] Don't include `timescale 1ns/10ps into my module?

[Neal B. <ndb...@gm...>]

When I convert my module to verilog with myhdl, it starts with:
`timescale 1ns/10ps

How do I avoid writing that?  I want to set this in the testbench and I 
think it would be a problem to try to set it in the module as well (I'm a 
verilog newb, so I might be misunderstanding something here).

Re: [myhdl-list] Don't include `timescale 1ns/10ps into my module?

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> When I convert my module to verilog with myhdl, it starts with:
> `timescale 1ns/10ps
> 
> How do I avoid writing that?  I want to set this in the testbench and I 
> think it would be a problem to try to set it in the module as well (I'm a 
> verilog newb, so I might be misunderstanding something here).

It should not normally be a problem. Verilog understands the directive
on a per-module level and I think it's considered good practice
to set it in each module.

At some point, I introduced it because I needed it for some 
user-defined code to work properly.

I now see that it's not documented that you can actually set your
desired timescale using the toVerilog.timescale attribute. However,
it's not currently possible to disable it.

This could be changed: the default could be not to include a timescale
directive and only include it if the user sets the attribute.
Feedback welcome.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] Don't include `timescale 1ns/10ps into my module?

[Christopher F. <chr...@gm...>]

On Tue, Mar 3, 2009 at 2:48 PM, Jan Decaluwe <ja...@ja...> wrote:

> Neal Becker wrote:
> > When I convert my module to verilog with myhdl, it starts with:
> > `timescale 1ns/10ps
>


>
> This could be changed: the default could be not to include a timescale
> directive and only include it if the user sets the attribute.
> Feedback welcome.
>

 Yes, I like that option.  Default it is disabled and only enabled when the
user adds it via the attribute.

The default case would be that Verilog and VHDL are similiar, correct?