myhdl-list

[myhdl-list] assertion error in toVerilog

[Neal B. <ndb...@gm...>]

Traceback (most recent call last):
  File "test3.py", line 65, in <module>
    tb = toVerilog (testbench)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", line
115, in __call__
    genlist = _analyzeGens(arglist, h.absnames)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
160, in _analyzeGens
    compiler.walk(ast, v)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 106, in walk
    walker.preorder(tree, visitor)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 63, in preorder
    self.dispatch(tree, *args) # XXX *args make sense?
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
939, in visitModule
    self.visit(node.node)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
    self.dispatch(child, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
998, in visitFunction
    self.visit(node.code)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
    self.dispatch(child, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
486, in visitAugAssign
    self.visit(node.node, _access.INOUT)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
632, in visitGetattr
    self.visit(node.expr, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
743, in visitName
    raise AssertionError
AssertionError

Here is code:
from myhdl import Signal, always, intbv, Simulation, delay, toVerilog,
traceSignals, always_comb, instance



def Counter (count, clock, n):
    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

        print "count:", count
    return cntLogic

def accum (x, result, count, clock, n):
    _sum = Signal (intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        _sum.next += x
        if count == n-1:
            ##print 'count:', count, 'sum:', _sum
            result.next = _sum
            _sum.next = 0

    return accum_logic

def Decimator (clock, x, n, count, result):
    cnt1 = Counter (count, clock, n)
    acc1 = accum (x, result, count, clock, n)
    return cnt1, acc1

def testbench():
    HALF_PERIOD = delay(1)

    n = 16
    x = Signal (intbv(0)[4:])
    #clock = Signal()
    clock = Signal (intbv(0)[1:])
    result = Signal(intbv()[8:])
    count = Signal (intbv(0)[4:])
    
    decimator1 = Decimator (clock, x, n, count, result)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            x.next = 1
        
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'x:', x, 'count:', count, 'result:', result

    return clockGen, stimulus, decimator1, monitor


tb = toVerilog (testbench)

def main():
    Simulation(tb).run(50)

if __name__ == "__main__":
    main()

Any ideas?

Re: [myhdl-list] assertion error in toVerilog

[Neal B. <ndb...@gm...>]

It seems putting:
_anaylyze.py:743
               print access
                raise AssertionError

reveals:
INOUT

Re: [myhdl-list] assertion error in toVerilog

[Christopher F. <chr...@gm...>]

>
> tb = toVerilog (testbench)
>
> def main():
>    Simulation(tb).run(50)
>
> if __name__ == "__main__":
>    main()
>
> Any ideas?
>
>
Not sure if this is your specific issue, you may want to try and only
convert the design to Verilog.  Converting testbenches is a newer feature of
the latest release.  Below is an snippet of an example only converting the
design and not the testbench.  There are a bunch of examples in the cookbook
and the user project area.

    #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    # Signals
    clk = Signal(False)
    rst = Signal(False)

    x = Signal(intbv(0, min=-L, max=L))
    y = Signal(intbv(0, min=minV, max=maxV))

    dvi = Signal(True)
    dvo = Signal(False)

    xcnt  = Signal(0)
    N_CLK = 0

    #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    # Instantiate MyHDL simulation and coversion functions
    if run == 'trace':
        dut = traceSignals(cic, clk, rst, x, dvi, y, dvo, M, D, R)
    elif run == 'ver':
        toVerilog(cic, clk, rst, x, dvi, y, dvo, M, D, R)
        return None
    elif run == 'vhd':
        toVHDL(cic, clk, rst, x, dvi, y, dvo, M, D, R)
        return None
    else:
        dut = cic(clk, rst, x, dvi, y, dvo, M, D, R)

Re: [myhdl-list] assertion error in toVerilog

[Christopher F. <chr...@gm...>]

from myhdl import *

def Counter (count, clock, n):
    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

    return cntLogic

def accum (x, result, count, clock, n):
    _sum = Signal(intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        _sum.next = _sum + x
        if count == n-1:
            #result.next = _sum
            _sum.next = 0

    @always (clock.posedge)
    def rtl():
        if count == n-1:
            result.next = _sum
            
    return accum_logic, rtl

def Decimator (clock, x, n, count, result):
    cnt1 = Counter(count, clock, n)
    acc1 = accum(x, result, count, clock, n)
    return cnt1, acc1

if __name__ == '__main__':
    n = 16
    x      = Signal(intbv(0)[4:])
    clock  = Signal(False)
    result = Signal(intbv(0)[8:])
    count  = Signal(intbv(0)[4:])
    
    #dut = Decimator (clock, x, n, count, result)
    toVerilog(Decimator, clock, x, n, count, result)

Re: [myhdl-list] assertion error in toVerilog

[Neal B. <ndb...@gm...>]

Christopher Felton wrote:

>>
>>    @always (clock.posedge)
>>    def accum_logic():
>>        _sum.next += x
>>        if count == n-1:
>>            ##print 'count:', count, 'sum:', _sum
>>            result.next = _sum
>>            _sum.next = 0
>>
>>    return accum_logic
>>
>> Any ideas?
> 
> 
> The problem is the _sum.next += x
> 
> Change to _sum.next = _sum + x
> 
> Attached is the code that I successfully converted.
Thank you so much for your help!

2 questions:
1.
 python test3.py
** ToVerilogWarning: Output port is read internally: count

What does this mean and should I worry?  Any way to tell what lines of code 
this is coming from?

2.
I noticed you changed:
    @always (clock.posedge)
    def accum_logic():
        _sum.next = _sum + x
        if count == n-1:
            ##print 'count:', count, 'sum:', _sum
            result.next = _sum
            _sum.next = 0

   return accum_logic

to

   @always (clock.posedge) 
     def accum_logic(): 
         _sum.next = _sum + x 
         if count == n-1: 
             #result.next = _sum 
             _sum.next = 0 
 
     @always (clock.posedge) 
     def rtl(): 
         if count == n-1: 
             result.next = _sum 
             
     return accum_logic, rtl 
 
Any significance to this change?

Re: [myhdl-list] assertion error in toVerilog

[Christopher F. <chr...@gm...>]

>
>
> 2 questions:
> 1.
>  python test3.py
> ** ToVerilogWarning: Output port is read internally: count
>
> What does this mean and should I worry?  Any way to tell what lines of code
> this is coming from?


I did not scrutinize the Verilog output.  For this exercise I was content
when the converter ran without error.  I do not know what the error is with
out greping for the error string.


>
>
> 2.
> I noticed you changed:
>     @always (clock.posedge)
>    def accum_logic():
>         _sum.next = _sum + x
>         if count == n-1:
>            ##print 'count:', count, 'sum:', _sum
>            result.next = _sum
>            _sum.next = 0
>
>   return accum_logic
>
> to
>
>   @always (clock.posedge)
>     def accum_logic():
>          _sum.next = _sum + x
>         if count == n-1:
>             #result.next = _sum
>             _sum.next = 0
>
>     @always (clock.posedge)
>     def rtl():
>         if count == n-1:
>             result.next = _sum
>
>     return accum_logic, rtl
>
> Any significance to this change?
>
>
Sorry, the changes are not significant.  I was just testing a couple
different things.  I randomly tried a couple things before analyzing the
signal that was being asserted (printing the sig in _analyze.py).  I never
put the code back to the original structure.  Before modifying _analyze.py
to print more info I was trying to get some more information.

Re: [myhdl-list] assertion error in toVerilog

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Christopher Felton wrote:
> 
>>>    @always (clock.posedge)
>>>    def accum_logic():
>>>        _sum.next += x
>>>        if count == n-1:
>>>            ##print 'count:', count, 'sum:', _sum
>>>            result.next = _sum
>>>            _sum.next = 0
>>>
>>>    return accum_logic
>>>
>>> Any ideas?
>>
>> The problem is the _sum.next += x
>>
>> Change to _sum.next = _sum + x
>>
>> Attached is the code that I successfully converted.
> Thank you so much for your help!
> 
> 2 questions:
> 1.
>  python test3.py
> ** ToVerilogWarning: Output port is read internally: count
> 
> What does this mean and should I worry?  Any way to tell what lines of code 
> this is coming from?

It means that count is an output port that is not only written,
but also read internally.

In Verilog and MyHDL, this is allowed without problems, although some
may argue it's not very clean. In VHDL, you cannot do this unless the output
port is declared as "inout", which some designers may want to avoid. Hence
the warning, so you know.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] assertion error in toVerilog

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Traceback (most recent call last):
>   File "test3.py", line 65, in <module>
>     tb = toVerilog (testbench)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", line
> 115, in __call__
>     genlist = _analyzeGens(arglist, h.absnames)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 160, in _analyzeGens
>     compiler.walk(ast, v)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 106, in walk
>     walker.preorder(tree, visitor)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 63, in preorder
>     self.dispatch(tree, *args) # XXX *args make sense?
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 939, in visitModule
>     self.visit(node.node)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
>     self.dispatch(child, *args)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 998, in visitFunction
>     self.visit(node.code)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
>     self.dispatch(child, *args)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 486, in visitAugAssign
>     self.visit(node.node, _access.INOUT)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 632, in visitGetattr
>     self.visit(node.expr, *args)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 743, in visitName
>     raise AssertionError
> AssertionError
> 
> Here is code:
> from myhdl import Signal, always, intbv, Simulation, delay, toVerilog,
> traceSignals, always_comb, instance
> 
> 
> 
> def Counter (count, clock, n):
>     @always (clock.posedge)
>     def cntLogic():
>         if count == n-1:
>             count.next = 0
>         else:
>             count.next = count + 1
> 
>         print "count:", count
>     return cntLogic
> 
> def accum (x, result, count, clock, n):
>     _sum = Signal (intbv(0)[8:])
>     
>     @always (clock.posedge)
>     def accum_logic():
>         _sum.next += x
>         if count == n-1:
>             ##print 'count:', count, 'sum:', _sum
>             result.next = _sum
>             _sum.next = 0
> 
>     return accum_logic
> 
> def Decimator (clock, x, n, count, result):
>     cnt1 = Counter (count, clock, n)
>     acc1 = accum (x, result, count, clock, n)
>     return cnt1, acc1
> 
> def testbench():
>     HALF_PERIOD = delay(1)
> 
>     n = 16
>     x = Signal (intbv(0)[4:])
>     #clock = Signal()
>     clock = Signal (intbv(0)[1:])
>     result = Signal(intbv()[8:])
>     count = Signal (intbv(0)[4:])
>     
>     decimator1 = Decimator (clock, x, n, count, result)
>     
>     @always(HALF_PERIOD)
>     def clockGen():
>         clock.next = not clock
> 
>     @instance
>     def stimulus():
>         while (1):
>             yield clock.posedge
>             x.next = 1
>         
>     @instance
>     def monitor():
>         while 1:
>             yield clock.posedge
>             print 'x:', x, 'count:', count, 'result:', result
> 
>     return clockGen, stimulus, decimator1, monitor
> 
> 
> tb = toVerilog (testbench)
> 
> def main():
>     Simulation(tb).run(50)
> 
> if __name__ == "__main__":
>     main()
> 
> Any ideas?

Yes:
      _sum.next += x

has no equivalent in VHDL or Verilog, as it is equivalent to:

     _sum.next = _sum.next + x

In other words, it updates the future value by adding to the future value.
(I'm not sure it's useful in MyHDL either.)

So it cannot be converted. However, this problem should be indicated with
a proper exception and error message, and not with an assertion, so the
AssertionError is a bug.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] assertion error in toVerilog

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Neal Becker wrote:
>> Traceback (most recent call last):
>>   File "test3.py", line 65, in <module>
>>     tb = toVerilog (testbench)
>>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", line
>> 115, in __call__
>>     genlist = _analyzeGens(arglist, h.absnames)
>>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
>> 160, in _analyzeGens
>>     compiler.walk(ast, v)
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 106, in walk
>>     walker.preorder(tree, visitor)
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 63, in preorder
>>     self.dispatch(tree, *args) # XXX *args make sense?
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>>     return meth(node, *args)
>>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
>> 939, in visitModule
>>     self.visit(node.node)
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>>     return meth(node, *args)
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
>>     self.dispatch(child, *args)
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>>     return meth(node, *args)
>>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
>> 998, in visitFunction
>>     self.visit(node.code)
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>>     return meth(node, *args)
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
>>     self.dispatch(child, *args)
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>>     return meth(node, *args)
>>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
>> 486, in visitAugAssign
>>     self.visit(node.node, _access.INOUT)
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>>     return meth(node, *args)
>>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
>> 632, in visitGetattr
>>     self.visit(node.expr, *args)
>>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>>     return meth(node, *args)
>>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
>> 743, in visitName
>>     raise AssertionError
>> AssertionError
>>
>> Here is code:
>> from myhdl import Signal, always, intbv, Simulation, delay, toVerilog,
>> traceSignals, always_comb, instance
>>
>>
>>
>> def Counter (count, clock, n):
>>     @always (clock.posedge)
>>     def cntLogic():
>>         if count == n-1:
>>             count.next = 0
>>         else:
>>             count.next = count + 1
>>
>>         print "count:", count
>>     return cntLogic
>>
>> def accum (x, result, count, clock, n):
>>     _sum = Signal (intbv(0)[8:])
>>     
>>     @always (clock.posedge)
>>     def accum_logic():
>>         _sum.next += x
>>         if count == n-1:
>>             ##print 'count:', count, 'sum:', _sum
>>             result.next = _sum
>>             _sum.next = 0
>>
>>     return accum_logic
>>
>> def Decimator (clock, x, n, count, result):
>>     cnt1 = Counter (count, clock, n)
>>     acc1 = accum (x, result, count, clock, n)
>>     return cnt1, acc1
>>
>> def testbench():
>>     HALF_PERIOD = delay(1)
>>
>>     n = 16
>>     x = Signal (intbv(0)[4:])
>>     #clock = Signal()
>>     clock = Signal (intbv(0)[1:])
>>     result = Signal(intbv()[8:])
>>     count = Signal (intbv(0)[4:])
>>     
>>     decimator1 = Decimator (clock, x, n, count, result)
>>     
>>     @always(HALF_PERIOD)
>>     def clockGen():
>>         clock.next = not clock
>>
>>     @instance
>>     def stimulus():
>>         while (1):
>>             yield clock.posedge
>>             x.next = 1
>>         
>>     @instance
>>     def monitor():
>>         while 1:
>>             yield clock.posedge
>>             print 'x:', x, 'count:', count, 'result:', result
>>
>>     return clockGen, stimulus, decimator1, monitor
>>
>>
>> tb = toVerilog (testbench)
>>
>> def main():
>>     Simulation(tb).run(50)
>>
>> if __name__ == "__main__":
>>     main()
>>
>> Any ideas?
> 
> Yes:
>       _sum.next += x
> 
> has no equivalent in VHDL or Verilog, as it is equivalent to:
> 
>      _sum.next = _sum.next + x
> 
> In other words, it updates the future value by adding to the future value.
> (I'm not sure it's useful in MyHDL either.)
> 
> So it cannot be converted. However, this problem should be indicated with
> a proper exception and error message, and not with an assertion, so the
> AssertionError is a bug.

This has been fixed in development.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com