myhdl-list

[myhdl-list] toVHDL - lazy debug?

[Jan C. <jen...@mu...>]

I have a convoluted module which passes outline
testing, and converts to ~500 lines of Verilog,
but will not convert to VHDL. 

On VHDL conversion failure the call stack has
entries for toVHDL and ast, and ends with the
message: 

"AttributeError: 'NoneType' object has no
attribute 'size'"

The resulting .vhd file has a complete list of
signals, but no code. 


I'd prefer not to hack the code apart to find the
problem, are there any simpler ways of
unravelling this problem?


Jan Coombs. 
--

toVHDL
Traceback (most recent call last):
  File "./testStackCacheHandles.py", line 253, in
<module> clk,coreClkEn,rst, NumHndls)
  File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 203, in __call__ _convertGens(genlist,
siglist, memlist, vfile) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 461, in _convertGens v.visit(tree) File
"/usr/lib/python2.7/ast.py", line 241, in visit
return visitor(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 1224, in visit_Module self.visit(stmt) File
"/usr/lib/python2.7/ast.py", line 241, in visit
return visitor(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 1606, in visit_FunctionDef
self.visit_stmt(node.body) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 1432, in visit_stmt self.visit(stmt) File
"/usr/lib/python2.7/ast.py", line 241, in visit
return visitor(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 872, in visit_Assign self.visit(rhs) File
"/usr/lib/python2.7/ast.py", line 241, in visit
return visitor(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 644, in visit_BinOp self.BitOp(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 729, in BitOp self.visit(node.left) File
"/usr/lib/python2.7/ast.py", line 241, in visit
return visitor(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 1003, in visit_Compare ns = node.vhd.size
AttributeError: 'NoneType' object has no
attribute 'size'

Re: [myhdl-list] toVHDL - lazy debug?

[Jose M. G. C. <ch...@gm...>]

Dear Jan,

I think this should come from a non initialized Signal, or some forgot .next.

In any case, I have this lines just after the visit_Compare:

    def visit_Compare(self, node):
        node.vhd = vhd_boolean()
        self.generic_visit(node)
        left, op, right = node.left, node.ops[0], node.comparators[0]
        if left.vhd is None:
            print(ast.dump(node))

The dump should provide you some hints.

	Best,

		Jose M.

> El 15/5/2015, a las 16:44, Jan Coombs <jen...@mu...> escribió:
> 
> I have a convoluted module which passes outline
> testing, and converts to ~500 lines of Verilog,
> but will not convert to VHDL. 
> 
> On VHDL conversion failure the call stack has
> entries for toVHDL and ast, and ends with the
> message: 
> 
> "AttributeError: 'NoneType' object has no
> attribute 'size'"
> 
> The resulting .vhd file has a complete list of
> signals, but no code. 
> 
> 
> I'd prefer not to hack the code apart to find the
> problem, are there any simpler ways of
> unravelling this problem?
> 
> 
> Jan Coombs. 
> --
> 
> toVHDL
> Traceback (most recent call last):
>  File "./testStackCacheHandles.py", line 253, in
> <module> clk,coreClkEn,rst, NumHndls)
>  File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 203, in __call__ _convertGens(genlist,
> siglist, memlist, vfile) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 461, in _convertGens v.visit(tree) File
> "/usr/lib/python2.7/ast.py", line 241, in visit
> return visitor(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 1224, in visit_Module self.visit(stmt) File
> "/usr/lib/python2.7/ast.py", line 241, in visit
> return visitor(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 1606, in visit_FunctionDef
> self.visit_stmt(node.body) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 1432, in visit_stmt self.visit(stmt) File
> "/usr/lib/python2.7/ast.py", line 241, in visit
> return visitor(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 872, in visit_Assign self.visit(rhs) File
> "/usr/lib/python2.7/ast.py", line 241, in visit
> return visitor(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 644, in visit_BinOp self.BitOp(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 729, in BitOp self.visit(node.left) File
> "/usr/lib/python2.7/ast.py", line 241, in visit
> return visitor(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 1003, in visit_Compare ns = node.vhd.size
> AttributeError: 'NoneType' object has no
> attribute 'size'
> 
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Re: [myhdl-list] toVHDL - lazy debug?

[Jan C. <jen...@mu...>]

On Fri, 15 May 2015 18:07:49 -0400
"Jose M. Gomez Cama" <ch...@gm...> wrote:

> Dear Jan,
> 
> I think this should come from a non initialized
> Signal, or some forgot .next.
> 
> In any case, I have this lines just after the
> visit_Compare:
> 
>     def visit_Compare(self, node):
>         node.vhd = vhd_boolean()
>         self.generic_visit(node)
>         left, op, right = node.left,
> node.ops[0], node.comparators[0] if left.vhd is
> None: print(ast.dump(node))
> 
> The dump should provide you some hints.

Thanks, all fixed.  I had to put the dump at the
indicated line number, ~1006, and remove the
conditional, as I could not adapt it quickly. 

The problem was consistent use of bitwise
operators in a boolean expression. 

I noticed that if there is a mixture of logical
and boolean operators you get a nice error
message:

"myhdl.ConversionError: in
file /.../bcDscHndls.py, line 214: Not supported:
non-boolean argument in logical operator"

but no help for the completely stupid! 

Help much appreciated, now I'll check the rest of
this old code set. 

Kind regards, Jan Coombs. 
-- 

> > El 15/5/2015, a las 16:44, Jan Coombs
> > 
> > I have a convoluted module which passes
> > outline testing, and converts to ~500 lines
> > of Verilog, but will not convert to VHDL. 
> > 
> > On VHDL conversion failure the call stack has
> > entries for toVHDL and ast, and ends with the
> > message: 
> > 
> > "AttributeError: 'NoneType' object has no
> > attribute 'size'"
> > 
> > The resulting .vhd file has a complete list of
> > signals, but no code. 
> > 
> > Jan Coombs.