myhdl-list

[myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

This may be of interest. My verilog-wrapping and WISHBONE modules are
still experimental, but at some point I'd like to share them:

http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> This may be of interest. My verilog-wrapping and WISHBONE modules are
> still experimental, but at some point I'd like to share them:
> 
> http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81

George:

It's about time to announce all your achievements and the project page
in comp.arch.fpga. I would think there is a large interested
public over there (including FPGA vendors watching carefully.)

Or do you prefer me to do it :-) ?

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

> George Pantazopoulos wrote:
>> This may be of interest. My verilog-wrapping and WISHBONE modules are
>> still experimental, but at some point I'd like to share them:
>>
>> http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81
>
> George:
>
> It's about time to announce all your achievements and the project page
> in comp.arch.fpga. I would think there is a large interested
> public over there (including FPGA vendors watching carefully.)
>
> Or do you prefer me to do it :-) ?
>

I'll take that as a complement, thanks! :-) Sounds like you have more
"street cred" in comp.arch.fpga right now, so I think you'd be a better
choice. I don't think I'm ready just yet, but feel free to ask again :-)

For my Verilog wrapping to be fully useful, I need MyHDL to do something =
new.

The problem right now is that I need to manually add any external Verilog
files to Xilinx ISE's project manager or else the MyHDL output won't
synthesize due to missing modules.

I'd love for MyHDL to automate this by slurping up any Verilog
dependencies specified in the MyHDL code and including them with its own
Verilog output.

For example, I could give the toVerilog convertor a set of (verilog)
filenames, or even a directory name. It then reads in all those files and
combines them with the Verilog output. The "combining" is simply pasting
the  text in somehow with the MyHDL-generated Verilog; no interpretation
necessary.

This could be as simple as appending them all to the MyHDL Verilog output
file. Alternatively, it could create a seperate verilog output file or
files containing all the "dependencies". That way, the MyHDL output would
be completely ready to use, without the user needing external knowledge
about which Verilog files to include into their synthesis tool's project.

It sounds pretty simple. What do you think?

George



> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Losbergenlaan 16, B-3010 Leuven, Belgium
>      From Python to silicon:
>      http://myhdl.jandecaluwe.com
>
>
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--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Tom D. <TD...@di...>]

> For my Verilog wrapping to be fully useful, I need MyHDL to do something
> new.
>
> The problem right now is that I need to manually add any external Verilog
> files to Xilinx ISE's project manager or else the MyHDL output won't
> synthesize due to missing modules.
>
> I'd love for MyHDL to automate this by slurping up any Verilog
> dependencies specified in the MyHDL code and including them with its own
> Verilog output.
>

I would recommend a makefile or a python script to automate this process for 
you.

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

>> For my Verilog wrapping to be fully useful, I need MyHDL to do somethi=
ng
>> new.
>>
>> The problem right now is that I need to manually add any external
>> Verilog
>> files to Xilinx ISE's project manager or else the MyHDL output won't
>> synthesize due to missing modules.
>>
>> I'd love for MyHDL to automate this by slurping up any Verilog
>> dependencies specified in the MyHDL code and including them with its o=
wn
>> Verilog output.
>>
>
> I would recommend a makefile or a python script to automate this proces=
s
> for
> you.
>

I think your idea is reasonable, but having MyHDL handle it would be much
more powerful. It would allow MyHDL-wrapped Verilog modules to be treated
just like any other MyHDL module (from a synthesis standpoint anyway).

Also, the User-defined Verilog feature won't work because it would create
nested modules that I confirmed do NOT work in Xilinx ISE.

I believe it wouldn't be too hard to integrate this feature. It mainly
involves file reads and writes. No interpretation necessary.

I don't expect pure MyHDL simulation would be possible though, but
cosimulating with the user-included Verilog files should just work, right
Jan?

George

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Tom D. <TD...@di...>]

> Also, the User-defined Verilog feature won't work because it would create
> nested modules that I confirmed do NOT work in Xilinx ISE.
>

I don't understand what you are saying won't work in ISE. Could you provide an 
example?

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

>> Also, the User-defined Verilog feature won't work because it would
>> create
>> nested modules that I confirmed do NOT work in Xilinx ISE.
>>
>
> I don't understand what you are saying won't work in ISE. Could you
> provide an
> example?
>

The User-defined Verilog works great and just as advertised for inserting
module instantiations into the MyHDL-generated Verilog code. I didn't mea=
n
to imply it was broken in some way.

What I mean is that I can't use that feature to declare additional, neede=
d
modules because it is only capable of inserting stuff *inside* existing
modules.

Something like this is not legal Verilog:

-- Begin example ----------------------------

// MyHDL-generated module
module top(...);

 // Verilog component from open-source library.
 module core(...);
   ... stuff ...
 endmodule

 core CORE_INST(...);

endmodule
-- End example -----------------------------

What I need is something like this:

-- Begin example ----------------------------


// contents of core.v pasted in by MyHDL
module core(...);

endmodule


// MyHDL-generated top module
module top(...);

  cor CORE_INST(...);

endmodule

-- End example -----------------------------

The above might be better done with an `include "core.v" or maybe an
`include "myhdl_verilog_deps.v" or something to that effect. I'm not sure
right now, and my Verilog skills could still use some sharpening.

George

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Tom D. <TD...@di...>]

On Tuesday 26 September 2006 18:09, George Pantazopoulos wrote:
> >> Also, the User-defined Verilog feature won't work because it would
> >> create
> >> nested modules that I confirmed do NOT work in Xilinx ISE.
> >
> > I don't understand what you are saying won't work in ISE. Could you
> > provide an
> > example?
>
> The User-defined Verilog works great and just as advertised for inserting
> module instantiations into the MyHDL-generated Verilog code. I didn't mean
> to imply it was broken in some way.
>
> What I mean is that I can't use that feature to declare additional, needed
> modules because it is only capable of inserting stuff *inside* existing
> modules.

I see what you are saying. I would still let ISE compile the files separately. 
That is the normal way of doing it and really doesn't cause any trouble.

Tom

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> On Tuesday 26 September 2006 18:09, George Pantazopoulos wrote:
> 
>>>>Also, the User-defined Verilog feature won't work because it would
>>>>create
>>>>nested modules that I confirmed do NOT work in Xilinx ISE.
>>>
>>>I don't understand what you are saying won't work in ISE. Could you
>>>provide an
>>>example?
>>
>>The User-defined Verilog works great and just as advertised for inserting
>>module instantiations into the MyHDL-generated Verilog code. I didn't mean
>>to imply it was broken in some way.
>>
>>What I mean is that I can't use that feature to declare additional, needed
>>modules because it is only capable of inserting stuff *inside* existing
>>modules.
> 
> 
> I see what you are saying. I would still let ISE compile the files separately. 
> That is the normal way of doing it and really doesn't cause any trouble.

I agree with that. This thread is really about Verilog project
management and I don't think MyHDL should play a role in that.

Because of the way it works (elaborating and flattening hierarchy),
the convertor generates one single Verilog output file. This makes it
easy to set up simple projects. But that doesn't mean that having
everything in one big file is the proper way to do project management
in larger projects.

As a last resort, you always have the choice of writing your own
convenience function that concatenates files and call it right
after the conversion in your Python file. But personally I would
set up the project properly, tracking dependencies with make or
in whatever way a project environment like ISE does it.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com