myhdl-list

[myhdl-list] Lists of signals as synthesizable arguments

[Eric J. <jo...@MI...>]

I'm trying to construct modules that will take in lists of signals and
gang them together as address lines, where I don't want to manually
break out those signals or pre-invocation gang them into a single
signal. 

I can't for the life of me figure out how to do this -- basically, what
I want is 

from myhdl import *

def MyTestObject(listofsigs, myval):
    totallen = sum(len(x) for x in listofsigs)

    @always_comb
    def logic():
        myval.next = concat(*listofsigs)

    return logic

def MyTestObjectTwo(myval):
    listofsigs = [Signal(intbv(0)[4:]),
                  Signal(intbv(0)[6:])]

    to = MyTestObject(listofsigs, myval)
    return to


def test_MyTestObject():

    myval = Signal(intbv(0)[10:])

    toVerilog(MyTestObjectTwo, myval)
    

However, this complains that the signal elements don't have the same
bitwidth (not sure why?) When I use only a single signal I get: 

    Not supported: extra positional arguments

Which suggests that concat(*listofsigs) isn't going to work. 

I've looked at the "Conversion of lists of signals" in the 0.6
documentation, but I'm not entirely clear how its statements relate to
my problem. 

Anywho, this is part of a larger set of questions about what the "Right"
abstractions are for working with myHDL, which I'll leave for another
day. :)  Any help would be greatly appreciated, thanks again, 

		...Eric

Re: [myhdl-list] Lists of signals as synthesizable arguments

[Jan D. <ja...@ja...>]

Eric Jonas wrote:
> I'm trying to construct modules that will take in lists of signals and
> gang them together as address lines, where I don't want to manually
> break out those signals or pre-invocation gang them into a single
> signal.

I don't see a solution immediately. It seems that we are hitting
the boundaries here to what can be meaningfully converted and
mapped to Verilog. 


> I can't for the life of me figure out how to do this -- basically, what
> I want is 
> 
> from myhdl import *
> 
> def MyTestObject(listofsigs, myval):
>     totallen = sum(len(x) for x in listofsigs)
> 
>     @always_comb
>     def logic():
>         myval.next = concat(*listofsigs)
> 
>     return logic
> 
> def MyTestObjectTwo(myval):
>     listofsigs = [Signal(intbv(0)[4:]),
>                   Signal(intbv(0)[6:])]
> 
>     to = MyTestObject(listofsigs, myval)
>     return to
> 
> 
> def test_MyTestObject():
> 
>     myval = Signal(intbv(0)[10:])
> 
>     toVerilog(MyTestObjectTwo, myval)
>     
> 
> However, this complains that the signal elements don't have the same
> bitwidth (not sure why?) 

The crucial point is: is the list referenced inside generator
code or not? If it is, it is mapped to a Verilog memory. And for
Verilog memories, all elements have the same bit width. Hence
the restriction.

> When I use only a single signal I get: 
> 
>     Not supported: extra positional arguments
> 
> Which suggests that concat(*listofsigs) isn't going to work.

Correct. This is not supported by the convertor.
> 
> I've looked at the "Conversion of lists of signals" in the 0.6
> documentation, but I'm not entirely clear how its statements relate to
> my problem. 

The point is that, if a list is referenced inside a generator,
there are much more conversion restrictions than if it isn't.

I admit that the kind of modelling problem you bring up is relevant.
But to get it converted, if possible, will need some fresh ideas that
I don't see right now.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as an HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Lists of signals as synthesizable arguments

[Jan D. <ja...@ja...>]

Eric Jonas wrote:
> I'm trying to construct modules that will take in lists of signals and
> gang them together as address lines, where I don't want to manually
> break out those signals or pre-invocation gang them into a single
> signal. 

Eric,

please check whether the ConcatSignal would be a solution for
your problem:

http://www.myhdl.org/doku.php/meps:mep-105

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com