Hi All,I failed to reference the exchange between Dave & Clifford Wolf at
https://hackaday.io/project/7982-cat-board
The following is what appears in iceriver/catboard.v
SB_IO #(
.PIN_TYPE(6'b000001),
.PULLUP(1'b1)
) input_pin_1 (
.PACKAGE_PIN(reset_i),
.D_IN_0(reset)
); Thanks,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
On Tuesday, January 19, 2016 6:10 PM, Edward Vidal <dev...@sb...> wrote:
Hi Chris,
As you recall I asked you, if the file ice40_primitives.py from Dave's CAT-Board/tests
https://github.com/xesscorp/CAT-Board.git
needed to added to the rhea package.
I am doing some testing and created a file
jpeg-2000-test/pc_fast_blinker_jpeg/test_top_cat.py which
https://github.com/develone/jpeg-2000-test.git
is imported by ex_catboard_jpeg.py with the chgs below.
diff ex_catboard_jpeg.py pc_fast_blinker_jpeg/ex_catboard_jpeg.py
26c26
< from test_top_cat import dwt_top
---
> from test_top import dwt_top
48c48
< brd.add_port('reset_i', 'T2')
---
> brd.add_port('reset', 'T2')
Running the test_top_cat.py --test and looking at the reset & reset_i signals.
The signal reset is always hi.
The signal reset_i goes lo when driven by the simulation.
For XulA2-LX9 I used the pullup=True see the file
jpeg-2000-test/pc_fast_blinker_jpeg/ex_jpeg_xula2.py from the repository
https://github.com/develone/jpeg-2000-test.git/
This creates the xula2.ucf
#
NET "reset" LOC = "J14" | pullup ;
NET "si2" LOC = "M15" | pullup ;
NET "si1" LOC = "F16" | pullup ;
NET "si0" LOC = "E2" | pullup ;
NET "fB3" LOC = "J16" | pullup ;
NET "clock" LOC = "A9" ;
NET "fB1" LOC = "C16" | pullup ;
NET "ss0" LOC = "H1" | pullup ;
NET "fB0" LOC = "R7" | pullup ;
NET "si3" LOC = "K16" | pullup ;
NET "ld" LOC = "B1" ;
NET "pp0" LOC = "K15" ;
NET "fB2" LOC = "M16" | pullup ;
#
NET "clock" TNM_NET = "clock";
TIMESPEC "TS_clock" = PERIOD "clock" 83.3333333 ns HIGH 50%;
# Thanks,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
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