myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/26/2012 12:19 AM, Christopher Felton wrote:

>
> I don't know if if is really an incorrect use of the enums.  I believe
> most examples are to define an enum and then create a signal with the
> enum type.
>
>      tEnum = enum('One', 'Two', 'Three')
>      x = Signal(tEnum.One)
>
> The question is, should it be valid (convertible) to use enums as basic
> constants?

No, enum is in principle an abstract type for which the encoding
could be chosen as part of later optimization. Note that you
can choose between an number of encodings from myhdl (when
defining the enum) or you can leave it to synthesis later (at
least in VHDL where the enum is mapped to a VHDL enum).


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 26/05/12 00:28, Jan Coombs wrote:
> The /always_comb/ problem still shows in my processor code when
> using enums, but converts ok when constants are used:

The attached code shows a problem with using enum for state control 
inside an @always_comb process.  I have carefully cut this down 
from my working code to show just my conversion problem.

> Perhaps if I knew a little more of class notation I could have
> simple constants expressed in the same notation as enums, and
> simplify comparative testing.
I had a go at this, and it seems to produce the same errors as 
using enums.

Jan Coombs.
-- 

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 25/05/12 23:19, Christopher Felton wrote:
[snip]
> This is *not* the error that I reported earlier, that the enum cannot be
> used in an /always_comb/.

I had hoped that the short tests I posted earlier would shed some 
light on this, but they only seem to demonstrate irregular case 
conversion.

The /always_comb/ problem still shows in my processor code when 
using enums, but converts ok when constants are used:

   if usingEnums:
     ExST = enum('Fetch1','Fetch2','NewAddr','Skip',  \
                     'Gap','Broken', encoding='one_hot')
     execState, execNextState =   \
                 [Signal(ExST.Fetch1) for i in range(2)]
   else:
     ExstFetch1,ExstFetch2,ExstNewAddr,ExstSkip,  \
                           ExstGap,ExstBroken = range(6)
     execState, execNextState =   \
                [Signal(intbv(0)[4:]) for i in range(2)]

The rest of the enum/const switch presently needs manual editing, 
but in summary, by process of elimination I have found that:

Assigning an enum to execNextState in an always_comb block produces 
the error:
   Object type is not supported in this context: ExST

In the clocked block which latches the next state, and in three 
other blocks where the state variable is compared with a constant, 
(ExST.xxx) this error is reported:
   TypeError: int() argument must be a string or a number, not 
'EnumItem'

Perhaps if I knew a little more of class notation I could have 
simple constants expressed in the same notation as enums, and 
simplify comparative testing.

Jan Coombs
-- 

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/25/2012 4:45 PM, Jan Coombs wrote:
> On 25/05/12 22:22, Christopher Felton wrote:
>> On 5/25/2012 3:58 PM, Jan Decaluwe wrote:
>>> On 05/25/2012 02:54 PM, Christopher Felton wrote:
>> <snip>
>>
>>>
>>> How can key be defined, if the enum is defined inside the module?
>>
>> Good question, in the original example the enum was being used as
>> "constant" values.  And "key" was of type intbv.  The quick answer might
>> have been don't mix types?
>
> I didn't notice that until today, so fixed that, and posted two
> more samples.
>
> The original problem with enums was in some other code, so I will
> recheck that, and post a sample if the error has not been fixed.
>

I don't know if if is really an incorrect use of the enums.  I believe 
most examples are to define an enum and then create a signal with the 
enum type.

    tEnum = enum('One', 'Two', 'Three')
    x = Signal(tEnum.One)

The question is, should it be valid (convertible) to use enums as basic 
constants?

   tEnum = enum('One', 'Two', 'Three')
   b = intbv(1, min=0, max=10)
   b == tEnum.One

Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/25/2012 4:22 PM, Christopher Felton wrote:
> On 5/25/2012 3:58 PM, Jan Decaluwe wrote:
>> On 05/25/2012 02:54 PM, Christopher Felton wrote:
> <snip>
>
>>
>> How can key be defined, if the enum is defined inside the module?
>
> Good question, in the original example the enum was being used as
> "constant" values.  And "key" was of type intbv.  The quick answer might
> have been don't mix types?
>
> The odd thing I ran into is that it worked in the /always/ generator and
> not the /always_comb/.  Below is the complete example, you should be
> able to run it.
>
>>
>> Can you or Jan C provide me with a short but complete example
>> (including signal defs and conversion call) that fails?
>> I'll start thinking after that :-)
>>
>

This example for the most part is probably *bunk*.  I thought I had 
extracted a portion of a larger example, which I might have.  But the 
strange thing here isn't that the /always_comb/ didn't convert it is 
that the /always/ *did* convert.  I got the cause and effect backwards.

I would (should) have noticed this if I had created a test.

def test():
     clk = Signal(False)
     key = Signal(intbv(1, min=1, max=9))
     led = Signal(intbv(0)[8:])
     dip = Signal(intbv(0)[8:])

     @always(delay(2))
     def tb_clkgen():
         clk.next = not clk

     @instance
     def tb_stimulus():
         for ii in range(1,key.max):
             yield clk.posedge
             print("key %d led %d" % (key, led))
             key.next = ii
         raise StopSimulation

     Simulation((tb_clkgen, tb_stimulus)).run()

-------------
Output
-------------
key 1 led 0
key 1 led 0
key 2 led 0
key 3 led 0
key 4 led 0
key 5 led 0
key 6 led 0
key 7 led 0

-------------

Again, the odd behavior is with the /always/ generator conversion.  I 
believe, it created valid logic.  The converted code should simulate 
correctly while the MyHDL code doesn't.

This is *not* the error that I reported earlier, that the enum cannot be 
used in an /always_comb/.

Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 25/05/12 22:22, Christopher Felton wrote:
> On 5/25/2012 3:58 PM, Jan Decaluwe wrote:
>> On 05/25/2012 02:54 PM, Christopher Felton wrote:
> <snip>
>
>>
>> How can key be defined, if the enum is defined inside the module?
>
> Good question, in the original example the enum was being used as
> "constant" values.  And "key" was of type intbv.  The quick answer might
> have been don't mix types?

I didn't notice that until today, so fixed that, and posted two 
more samples.

The original problem with enums was in some other code, so I will 
recheck that, and post a sample if the error has not been fixed.

Jan Coombs
-- 

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/25/2012 3:58 PM, Jan Decaluwe wrote:
> On 05/25/2012 02:54 PM, Christopher Felton wrote:
<snip>

>
> How can key be defined, if the enum is defined inside the module?

Good question, in the original example the enum was being used as 
"constant" values.  And "key" was of type intbv.  The quick answer might 
have been don't mix types?

The odd thing I ran into is that it worked in the /always/ generator and 
not the /always_comb/.  Below is the complete example, you should be 
able to run it.

>
> Can you or Jan C provide me with a short but complete example
> (including signal defs and conversion call) that fails?
> I'll start thinking after that :-)
>

import myhdl
print myhdl.__version__
from myhdl import *

def case_ex1(clk, key, led):
     tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
     @always(clk.posedge)
     def hdl():
         if   key==tKey.UP:    led.next = 0xDE
         elif key==tKey.DOWN:  led.next = 0xCA
         elif key==tKey.LEFT:  led.next = 0xFB
         elif key==tKey.RIGHT: led.next = 0xAD
         else:                 led.next = 0x00

     return hdl

def case_ex2(key, led):
     tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
     @always_comb
     def hdl():
         if   key==tKey.UP:    led.next = 0xDE
         elif key==tKey.DOWN:  led.next = 0xCA
         elif key==tKey.LEFT:  led.next = 0xFB
         elif key==tKey.RIGHT: led.next = 0xAD
         else:                 led.next = 0x00

     return hdl

if __name__ == '__main__':
     clk = Signal(False)
     key = Signal(intbv(1, min=1, max=9))
     led = Signal(intbv(0)[8:])
     dip = Signal(intbv(0)[8:])

     print('Covert case_ex1')
     toVerilog(case_ex1, clk, key, led)
     toVHDL(case_ex1, clk, key, led)

     print('Convert case_ex2')
     toVerilog(case_ex2, key, led)
     toVHDL(case_ex2, key, led)


----------------
Output from run
----------------
   >> python case.py
   0.8dev
   Covert case_ex1
   Convert case_ex2
   Traceback (most recent call last):
     File "case.py", line 41, in <module>
       toVerilog(case_ex2, key, led)
_analyze.py", line 165, in _analyzeGens
     raise ConversionError(_error.UnsupportedType, n, info)
myhdl.ConversionError: File case.py, line 19: Object type is not 
supported in this context: tKey


Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 25/05/12 21:55, Jan Decaluwe wrote:
> On 05/25/2012 01:47 PM, Jan Coombs wrote:
>
>>>
>>> No, it was something else. Can you point me to the
>>> post/author of the other problem(s). I lost track a little
>>> but I will look into it with priority.
>>
>> Have attached short code sample. There was a problem using enums in @always_comb
>
> Not short, and example fails with ImportError.
>
Sorry for that, I am slowly getting quicker at stripping code.

These two are self-contained and small.  It seems to show 
irregularity in case generation, but does not show the problem 
where use of enum seemed illegal.

Thanks for the reply advice.

Jan Coombs.
-- 

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/25/2012 02:54 PM, Christopher Felton wrote:

>
>> I think your issue with using the enum() is in combination with the
>> always_comb decorator.  The enums don't seem to work in an always_comb?
>>    I didn't realize this limitation existed.  The following is the simple
>> example I used (one of your previous questions) to see if this was true
>> or not.
>>
>>       from myhdl import *
>>
>>       def case_ex1(clk, key, led):
>>           tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
>>           @always(clk.posedge)
>>           def hdl():
>>               if   key==tKey.UP:    led.next = 0xDE
>>               elif key==tKey.DOWN:  led.next = 0xCA
>>               elif key==tKey.LEFT:  led.next = 0xFB
>>               elif key==tKey.RIGHT: led.next = 0xAD
>>               else:                 led.next = 0x00
>>
>>           return hdl
>>
>>       def case_ex2(key, led):
>>           tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
>>           @always_comb
>>           def hdl():
>>               if   key==tKey.UP:    led.next = 0xDE
>>               elif key==tKey.DOWN:  led.next = 0xCA
>>               elif key==tKey.LEFT:  led.next = 0xFB
>>               elif key==tKey.RIGHT: led.next = 0xAD
>>               else:                 led.next = 0x00
>>
>>           return hdl
>>
>> In the above, the second does not convert correctly and fails the
>> freevar check in the _analyzeGens, determines the enum is an unsupported
>> type.

How can key be defined, if the enum is defined inside the module?

Can you or Jan C provide me with a short but complete example
(including signal defs and conversion call) that fails?
I'll start thinking after that :-)

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/25/2012 01:47 PM, Jan Coombs wrote:

>>
>> No, it was something else. Can you point me to the
>> post/author of the other problem(s). I lost track a little
>> but I will look into it with priority.
>
> Have attached short code sample. There was a problem using enums in @always_comb

Not short, and example fails with ImportError.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/25/2012 01:47 PM, Jan Coombs wrote:

>
> BTW, could you advise me if I should use reply/reply-all for posting.

reply

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/25/2012 6:09 AM, Jan Decaluwe wrote:
> On 05/24/2012 10:53 PM, Christopher Felton wrote:
>> On 5/24/2012 3:23 PM, Thoma HAUC wrote:
>>>        @always_comb
>>>        def outputenable():
>>>            if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC)
>>
>> I believe this is the issue.  There was a recent thread on this.  It
>> looks like enums fail in an always_comb.  A simple test case was
>> submitted recently.
>
> No, it was something else. Can you point me to the
> post/author of the other problem(s). I lost track a little
> but I will look into it with priority.
>
> Also, I propose to start using the bug tracker again, for
> formal bug reporting (after discussing it here preferably).
> Note that you can attach files to bug reports. I have
> done this for the bug that was just reported.
>

There have been a couple possible bugs reported.  It was my intent to 
submit patches with tests that exposed the issues.  Ah, such dreaming, 
time to work on fun things :)

Here is a snip from the a previous thread, using the enum in a 
always_comb didn't appear to work.  I tested quickly there could be a 
mistake on my part.

> I think your issue with using the enum() is in combination with the
> always_comb decorator.  The enums don't seem to work in an always_comb?
>   I didn't realize this limitation existed.  The following is the simple
> example I used (one of your previous questions) to see if this was true
> or not.
>
>      from myhdl import *
>
>      def case_ex1(clk, key, led):
>          tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
>          @always(clk.posedge)
>          def hdl():
>              if   key==tKey.UP:    led.next = 0xDE
>              elif key==tKey.DOWN:  led.next = 0xCA
>              elif key==tKey.LEFT:  led.next = 0xFB
>              elif key==tKey.RIGHT: led.next = 0xAD
>              else:                 led.next = 0x00
>
>          return hdl
>
>      def case_ex2(key, led):
>          tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
>          @always_comb
>          def hdl():
>              if   key==tKey.UP:    led.next = 0xDE
>              elif key==tKey.DOWN:  led.next = 0xCA
>              elif key==tKey.LEFT:  led.next = 0xFB
>              elif key==tKey.RIGHT: led.next = 0xAD
>              else:                 led.next = 0x00
>
>          return hdl
>
> In the above, the second does not convert correctly and fails the
> freevar check in the _analyzeGens, determines the enum is an unsupported
> type.

Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 25/05/12 12:09, Jan Decaluwe wrote:
> On 05/24/2012 10:53 PM, Christopher Felton wrote:
>> On 5/24/2012 3:23 PM, Thoma HAUC wrote:
>>>        @always_comb
>>>        def outputenable():
>>>            if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC)
>>
>> I believe this is the issue.  There was a recent thread on this.  It
>> looks like enums fail in an always_comb.  A simple test case was
>> submitted recently.
>
> No, it was something else. Can you point me to the
> post/author of the other problem(s). I lost track a little
> but I will look into it with priority.

Have attached short code sample.  There was a problem using enums 
in @always_comb

Chris F has also sample code to demo problem.

> Also, I propose to start using the bug tracker again, for
> formal bug reporting (after discussing it here preferably).
> Note that you can attach files to bug reports. I have
> done this for the bug that was just reported.

That sounds good.

BTW, could you advise me if I should use reply/reply-all for posting.

Jan Coombs

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/24/2012 10:53 PM, Christopher Felton wrote:
> On 5/24/2012 3:23 PM, Thoma HAUC wrote:
>>       @always_comb
>>       def outputenable():
>>           if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC)
>
> I believe this is the issue.  There was a recent thread on this.  It
> looks like enums fail in an always_comb.  A simple test case was
> submitted recently.

No, it was something else. Can you point me to the
post/author of the other problem(s). I lost track a little
but I will look into it with priority.

Also, I propose to start using the bug tracker again, for
formal bug reporting (after discussing it here preferably).
Note that you can attach files to bug reports. I have
done this for the bug that was just reported.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/24/2012 10:30 PM, Thoma HAUC wrote:
> Hi Jan,
>
> Are you able to print out the line number that raises the exception?
> Could you explain me what I did wrong?

I debugged this. You did nothing wrong - there was a bug
in case statement inference.

Workaround: use boolean tests on boolean variables
(if run, if not ack) for the moment.

Alternatively, I have fixed this in development, both
in the default maintenance branch as in 0.8-dev.

As a matter of style, it may be clearer to do all the
combinatorial decodes from a single always_comb, and
use default assignments in the begining, to specify
the most common value of a signal.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 25/05/12 05:51, Thoma HAUC wrote:
> Hi Jan,
>
> The function name has evolved.
> I found the issue but I am not able to explain the reason.
   . . .
Chris is correct; there is a problem using enums in @always_comb 
decorators which I missed when reading through your code.

I also have this problem, and have temporarily switched to using 
constants.

Jan Coombs

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Thoma H. <tho...@gm...>]

Hi Jan,

The function name has evolved.
I found the issue but I am not able to explain the reason.
In fact, when I replace:

            elif (state == StateEnum.SEND):
                if (run == INACTIVE):
                    state.next = StateEnum.SEND3

with:

            elif (state == StateEnum.SEND):
                if (run != ACTIVE):
                    state.next = StateEnum.SEND3

the exception will not longer raise and the verilog description seems 
correct.

Here are the source for the missing calls (visible in the traceback):
def convert(converter, architecture):
    clr = Signal(ACTIVE)
    clk = Signal(INACTIVE)
    run, ack = [Signal(INACTIVE) for i in range(2)]
    serialin = Signal(HIGH)
    datain = Signal(intbv(0)[8:])
    rdy = Signal(INACTIVE)
    oe = Signal(INACTIVE)
    serialout = Signal(HIGH)
    dataout = Signal(intbv(0)[8:])
    converter(architecture, clr, clk, run, ack, serialin, datain, rdy, 
oe, serialout, dataout)

def convert2verilog(architecture):
    convert(toVerilog, architecture)

convert2verilog(bidir_serial_master)

Thoma

> 
> If Chris is right, that it is a top level interface problem, then you
> will need to show the definitions for these: (clr, clk, run,
> ack, serialin, datain, rdy, oe, serialout, dataout) in order for anyone
> to re-create the problem, or to guesstimate it.
> 
> Niggle: the name of this source does not seem to match the one shown in
> your error messages. (convert2verilog(bidir_serial))
> 
> I am also struggling with this type of problem, so am very interested to
> understand yours, and would like to try techniques that have sometimes
> worked for me.
> 
> For anyone to have a quick look they will need source that demonstrates
> the problem with out having to re-create whatever might be missing.
> 
> Jan Coombs

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 24/05/12 21:30, Thoma HAUC wrote:
    . . .
> Here is the python source:
    . . .
> def bidir_serial_master(clr, clk, run, ack, serialin, datain, rdy, oe,
> serialout, dataout):

If Chris is right, that it is a top level interface problem, then 
you will need to show the definitions for these: (clr, clk, run, 
ack, serialin, datain, rdy, oe, serialout, dataout) in order for 
anyone to re-create the problem, or to guesstimate it.

Niggle: the name of this source does not seem to match the one 
shown in your error messages. (convert2verilog(bidir_serial))

I am also struggling with this type of problem, so am very 
interested to understand yours, and would like to try techniques 
that have sometimes worked for me.

For anyone to have a quick look they will need source that 
demonstrates the problem with out having to re-create whatever 
might be missing.

Jan Coombs

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/24/2012 3:23 PM, Thoma HAUC wrote:
>      @always_comb
>      def outputenable():
>          if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC)

I believe this is the issue.  There was a recent thread on this.  It 
looks like enums fail in an always_comb.  A simple test case was 
submitted recently.

Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Thoma H. <tho...@gm...>]

Hi Jan,

Are you able to print out the line number that raises the exception?
Could you explain me what I did wrong?

In advance many thanks

Here is the python source:

LOW, HIGH = bool(0), bool(1)
INACTIVE, ACTIVE = LOW, HIGH
StateEnum = enum('IDLE', 'HSYNC', 'SYNC', 'SYNC2', 'HADDR', 'ADDR', 
'ADDR2', 'ADDR3', 'HSEND', 'SEND', 'SEND2', 'SEND3', 'HRECV', 'RECV', 
'HRECV2', 'RECV2')

def bidir_serial_master(clr, clk, run, ack, serialin, datain, rdy, oe, 
serialout, dataout):

    state = Signal(StateEnum.IDLE)
    timeout = Signal(INACTIVE)
    count = Signal(intbv(0)[3:])
    inputreg = Signal(intbv(0)[8:])
    internaldata = Signal(intbv(0)[8:])
    int_rdy = Signal(INACTIVE)
    int_serialout = Signal(HIGH)

    @always_comb
    def copy():
        rdy.next = int_rdy
        serialout.next = int_serialout

    @always_comb
    def outputenable():
        if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC) or 
(state == StateEnum.SYNC2) or (state == StateEnum.HADDR) or (state == 
StateEnum.ADDR) or (state == StateEnum.ADDR2) or (state == 
StateEnum.ADDR3) or (state == StateEnum.HSEND) or (state == 
StateEnum.SEND) or (state == StateEnum.SEND2) or (state == 
StateEnum.SEND3)):
            oe.next = ACTIVE
        else:
            oe.next = INACTIVE

    @always_comb
    def ready():
        if ((state == StateEnum.IDLE) or (state == StateEnum.SYNC) or 
(state == StateEnum.ADDR) or (state == StateEnum.RECV2)):
            int_rdy.next = ACTIVE
        elif (state == StateEnum.SEND):
            int_rdy.next = run
        else:
            int_rdy.next = INACTIVE

    @always_comb
    def send_data():
        if ((state == StateEnum.ADDR) or (state == StateEnum.ADDR2) or 
(state == StateEnum.ADDR3) or (state == StateEnum.SEND) or (state == 
StateEnum.SEND2) or (state == StateEnum.SEND3)):
            int_serialout.next = internaldata[count]
        elif ((state == StateEnum.HADDR) or (state == StateEnum.HSEND) or 
(state == StateEnum.HRECV)):
            int_serialout.next = LOW
        else:
            int_serialout.next = HIGH

    @always(clk.posedge, clr.posedge)
    def storage():
        if (clr == ACTIVE):
            inputreg.next = 0
            internaldata.next = 0
        else:
            if ((ack == ACTIVE) and (int_rdy == ACTIVE)):
                inputreg.next = datain
            elif ((count == 7) and ((state == StateEnum.SYNC2) or (state 
== StateEnum.ADDR3) or (state == StateEnum.SEND2))):
                internaldata.next = inputreg
            if ((state == StateEnum.RECV) or (state == StateEnum.RECV2)):
                if (count == 7):
                    dataout.next[7:] = internaldata[7:]
                    dataout.next[7] = serialin
                else:
                    internaldata.next[count] = serialin

    @always(clk.posedge, clr.posedge)
    def counter():
        if (clr == ACTIVE):
            count.next = 0
            timeout.next = INACTIVE
        else:
            if ((state == StateEnum.SYNC) or (state == StateEnum.SYNC2) 
or (state == StateEnum.ADDR) or (state == StateEnum.ADDR2) or (state == 
StateEnum.ADDR3) or (state == StateEnum.SEND) or (state == 
StateEnum.SEND2) or (state == StateEnum.SEND3) or (state == 
StateEnum.RECV) or (state == StateEnum.RECV2)):
                count.next = (count + 1) % 8
            if (count == 6):
                timeout.next = ACTIVE
            if (count == 7):
                timeout.next = INACTIVE

    @always(clk.posedge, clr.posedge)
    def fsm():
        if (clr == ACTIVE):
            state.next = StateEnum.IDLE
        else:
            if (state == StateEnum.IDLE):
                if (run == ACTIVE):
                    state.next = StateEnum.SYNC
            elif (state == StateEnum.SYNC):
                if (ack == ACTIVE):
                    state.next = StateEnum.HSYNC
            elif (state == StateEnum.HSYNC):
                state.next = StateEnum.SYNC2
            elif (state == StateEnum.SYNC2):
                if (timeout == ACTIVE):
                    state.next = StateEnum.HADDR
            elif (state == StateEnum.HADDR):
                state.next = StateEnum.ADDR
            elif (state == StateEnum.ADDR):
                if (internaldata[0] == LOW):
                    state.next = StateEnum.ADDR2
                elif (ack == ACTIVE):
                    state.next = StateEnum.ADDR3
            elif (state == StateEnum.ADDR2):
                if (timeout == ACTIVE):
                        state.next = StateEnum.HRECV
            elif (state == StateEnum.ADDR3):
                if (timeout == ACTIVE):
                        state.next = StateEnum.HSEND
            elif (state == StateEnum.HSEND):
                state.next = StateEnum.SEND
            elif (state == StateEnum.SEND):
                if (run == INACTIVE):
                    state.next = StateEnum.SEND3
                elif (ack == ACTIVE):
                    state.next = StateEnum.SEND2
            elif (state == StateEnum.SEND2):
                if (timeout == ACTIVE):
                    state.next = StateEnum.HSEND
            elif (state == StateEnum.SEND3):
                if (timeout == ACTIVE):
                    state.next = StateEnum.IDLE
            elif (state == StateEnum.HRECV):
                state.next = StateEnum.RECV
            elif (state == StateEnum.RECV):
                if (timeout == ACTIVE):
                    if (run == ACTIVE):
                        state.next = StateEnum.HRECV2
                    else:
                        state.next = StateEnum.IDLE
            elif (state == StateEnum.HRECV2):
                state.next = StateEnum.RECV2
            elif (state == StateEnum.RECV2):
                if (ack == ACTIVE):
                    state.next = StateEnum.RECV
            else:
                state.next = StateEnum.IDLE

    return instances()

Thoma

> [texte cité caché]
_toVerilog.py",
> [texte cité caché]
------------------------------------------------------------------------------
> [texte cité caché]



------------------------------------------------------------------------------
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and 
threat landscape has changed and how IT managers can respond. Discussions 
will include endpoint security, mobile security and the latest in malware 
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Thoma H. <tho...@gm...>]

Hi Jan,

Are you able to print out the line number that raises the exception?
Could you explain me what I did wrong?

In advance many thanks

Here is the python source:

LOW, HIGH = bool(0), bool(1)
INACTIVE, ACTIVE = LOW, HIGH
StateEnum = enum('IDLE', 'HSYNC', 'SYNC', 'SYNC2', 'HADDR', 'ADDR', 
'ADDR2', 'ADDR3', 'HSEND', 'SEND', 'SEND2', 'SEND3', 'HRECV', 'RECV', 
'HRECV2', 'RECV2')

def bidir_serial_master(clr, clk, run, ack, serialin, datain, rdy, oe, 
serialout, dataout):

    state = Signal(StateEnum.IDLE)
    timeout = Signal(INACTIVE)
    count = Signal(intbv(0)[3:])
    inputreg = Signal(intbv(0)[8:])
    internaldata = Signal(intbv(0)[8:])
    int_rdy = Signal(INACTIVE)
    int_serialout = Signal(HIGH)

    @always_comb
    def copy():
        rdy.next = int_rdy
        serialout.next = int_serialout

    @always_comb
    def outputenable():
        if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC) or 
(state == StateEnum.SYNC2) or (state == StateEnum.HADDR) or (state == 
StateEnum.ADDR) or (state == StateEnum.ADDR2) or (state == 
StateEnum.ADDR3) or (state == StateEnum.HSEND) or (state == 
StateEnum.SEND) or (state == StateEnum.SEND2) or (state == 
StateEnum.SEND3)):
            oe.next = ACTIVE
        else:
            oe.next = INACTIVE

    @always_comb
    def ready():
        if ((state == StateEnum.IDLE) or (state == StateEnum.SYNC) or 
(state == StateEnum.ADDR) or (state == StateEnum.RECV2)):
            int_rdy.next = ACTIVE
        elif (state == StateEnum.SEND):
            int_rdy.next = run
        else:
            int_rdy.next = INACTIVE

    @always_comb
    def send_data():
        if ((state == StateEnum.ADDR) or (state == StateEnum.ADDR2) or 
(state == StateEnum.ADDR3) or (state == StateEnum.SEND) or (state == 
StateEnum.SEND2) or (state == StateEnum.SEND3)):
            int_serialout.next = internaldata[count]
        elif ((state == StateEnum.HADDR) or (state == StateEnum.HSEND) or 
(state == StateEnum.HRECV)):
            int_serialout.next = LOW
        else:
            int_serialout.next = HIGH

    @always(clk.posedge, clr.posedge)
    def storage():
        if (clr == ACTIVE):
            inputreg.next = 0
            internaldata.next = 0
        else:
            if ((ack == ACTIVE) and (int_rdy == ACTIVE)):
                inputreg.next = datain
            elif ((count == 7) and ((state == StateEnum.SYNC2) or (state 
== StateEnum.ADDR3) or (state == StateEnum.SEND2))):
                internaldata.next = inputreg
            if ((state == StateEnum.RECV) or (state == StateEnum.RECV2)):
                if (count == 7):
                    dataout.next[7:] = internaldata[7:]
                    dataout.next[7] = serialin
                else:
                    internaldata.next[count] = serialin

    @always(clk.posedge, clr.posedge)
    def counter():
        if (clr == ACTIVE):
            count.next = 0
            timeout.next = INACTIVE
        else:
            if ((state == StateEnum.SYNC) or (state == StateEnum.SYNC2) 
or (state == StateEnum.ADDR) or (state == StateEnum.ADDR2) or (state == 
StateEnum.ADDR3) or (state == StateEnum.SEND) or (state == 
StateEnum.SEND2) or (state == StateEnum.SEND3) or (state == 
StateEnum.RECV) or (state == StateEnum.RECV2)):
                count.next = (count + 1) % 8
            if (count == 6):
                timeout.next = ACTIVE
            if (count == 7):
                timeout.next = INACTIVE

    @always(clk.posedge, clr.posedge)
    def fsm():
        if (clr == ACTIVE):
            state.next = StateEnum.IDLE
        else:
            if (state == StateEnum.IDLE):
                if (run == ACTIVE):
                    state.next = StateEnum.SYNC
            elif (state == StateEnum.SYNC):
                if (ack == ACTIVE):
                    state.next = StateEnum.HSYNC
            elif (state == StateEnum.HSYNC):
                state.next = StateEnum.SYNC2
            elif (state == StateEnum.SYNC2):
                if (timeout == ACTIVE):
                    state.next = StateEnum.HADDR
            elif (state == StateEnum.HADDR):
                state.next = StateEnum.ADDR
            elif (state == StateEnum.ADDR):
                if (internaldata[0] == LOW):
                    state.next = StateEnum.ADDR2
                elif (ack == ACTIVE):
                    state.next = StateEnum.ADDR3
            elif (state == StateEnum.ADDR2):
                if (timeout == ACTIVE):
                        state.next = StateEnum.HRECV
            elif (state == StateEnum.ADDR3):
                if (timeout == ACTIVE):
                        state.next = StateEnum.HSEND
            elif (state == StateEnum.HSEND):
                state.next = StateEnum.SEND
            elif (state == StateEnum.SEND):
                if (run == INACTIVE):
                    state.next = StateEnum.SEND3
                elif (ack == ACTIVE):
                    state.next = StateEnum.SEND2
            elif (state == StateEnum.SEND2):
                if (timeout == ACTIVE):
                    state.next = StateEnum.HSEND
            elif (state == StateEnum.SEND3):
                if (timeout == ACTIVE):
                    state.next = StateEnum.IDLE
            elif (state == StateEnum.HRECV):
                state.next = StateEnum.RECV
            elif (state == StateEnum.RECV):
                if (timeout == ACTIVE):
                    if (run == ACTIVE):
                        state.next = StateEnum.HRECV2
                    else:
                        state.next = StateEnum.IDLE
            elif (state == StateEnum.HRECV2):
                state.next = StateEnum.RECV2
            elif (state == StateEnum.RECV2):
                if (ack == ACTIVE):
                    state.next = StateEnum.RECV
            else:
                state.next = StateEnum.IDLE

    return instances()

Thoma

> Looks like there is an upfront error check missing,
> could you post your code or a simplified version that exposes the error?
> 
> On 05/24/2012 08:43 PM, Thoma HAUC wrote:
>> Hi Tom,
>>
>> I already simulated the design without any issue.
>> The exception raises only during verilog generation process.
>>
>> Thoma
>>
>>> Not sure but have you simulated it in MyHDL? Usually that will help
>>> expose problems better than trying to go directly to Verilog.
>>>
>>> On 05/21/2012 03:54 PM, Thoma HAUC wrote:
>>>> Hi,
>>>>
>>>> I am new to myHDL and it seems to be a powerful tool.
>>>> Today, I need some help to locate the reason of the below exception.
>>>> Because there are no clue to indicate the line of the issue, I am
>>>> currently blocked in my evaluation of myHDL.
>>>>
>>>> Thank you in advance.
>>>>
>>>> Thoma
>>>>
>>>> Traceback (most recent call last):
>>>>     File "bidir_serial.py", line 209, in<module>
>>>>       convert2verilog(bidir_serial)
>>>>     File "bidir_serial.py", line 200, in convert2verilog
>>>>       convert(toVerilog, architecture)
>>>>     File "bidir_serial.py", line 194, in convert
>>>>       converter(architecture, clr, clk, run, ld, datain, rdy,
>>>>       serialout)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/
_toVerilog.py",
>>>> line 142, in __call__
>>>>       genlist = _analyzeGens(arglist, h.absnames)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 174, in _analyzeGens
>>>>       v.visit(tree)
>>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>>       return visitor(node)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 1078, in visit_Module
>>>>       self.generic_visit(node)
>>>>     File "/usr/lib/python2.7/ast.py", line 249, in generic_visit
>>>>       self.visit(item)
>>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>>       return visitor(node)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 1154, in visit_FunctionDef
>>>>       self.visit(n)
>>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>>       return visitor(node)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 744, in visit_If
>>>>       self.visitList(node.else_)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>>>     line
>>>> 161, in visitList
>>>>       self.visit(n)
>>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>>       return visitor(node)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 740, in visit_If
>>>>       self.visitList(suite)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>>>     line
>>>> 161, in visitList
>>>>       self.visit(n)
>>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>>       return visitor(node)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 770, in visit_If
>>>>       if (len(choices) == _getNritems(var1.obj)) or node.else_:
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 407, in _getNritems
>>>>       raise TypeError("Unexpected type")
>>>> TypeError: Unexpected type
>>
>>
>> 
------------------------------------------------------------------------------
>> Live Security Virtual Conference Exclusive live event will cover all
>> the ways today's security and threat landscape has changed and how IT
>> managers can respond. Discussions will include endpoint security,
>> mobile security and the latest in malware threats.
>> http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/

Re: [myhdl-list] Restrictions for conversion

[Jan D. <ja...@ja...>]

On 05/24/2012 06:27 PM, Norbo wrote:

> I completly agree with the 'X' but i am not so sure about the 'U'

Ok, but note that Verilog has only X, and MyHDL has to cater for
both :-)

In general, this type of problem is a real issue: we have to
support both HDLs at the back end, including their pecularities
and restrictions, and furthermore we poor open source guys have
take into account the restrictions of commercial tools!

> But i came to understand that the 'U' concept, kind of involves the 'X'
> concept
> and that the 'X' concept is not compatible with the intbv() integer
> concept, especially when
> it comes to operaters like "&" or "|".
>
> So in the end i kind of have to thank you for stopping me on continue
> implementing on something which is not reasonable feasible the way i
> thought.

Well, I think you were finding out that you know where you
start but you don't were you will end - I went through the
experience before.

Note that I haven't claimed that there is no issue - there is.
I also don't want to say categorically that "None" has no role
to play - I have used it for tristate representation. I only
said that supporting None in intbv is not a good idea.

In a situation like this, I think we should try to think out
of the box and innovate. Not try to mimic what exists,
because it's all broken in some way, but come up with
a better solution. I have some ideas but I need to think
a bit longer first.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/24/2012 1:43 PM, Thoma HAUC wrote:
> Hi Tom,
>
> I already simulated the design without any issue.
> The exception raises only during verilog generation process.
>
> Thoma
>
>> Not sure but have you simulated it in MyHDL? Usually that will help
>> expose problems better than trying to go directly to Verilog.
>>
>> On 05/21/2012 03:54 PM, Thoma HAUC wrote:
>>> Hi,
>>>
>>> I am new to myHDL and it seems to be a powerful tool.
>>> Today, I need some help to locate the reason of the below exception.
>>> Because there are no clue to indicate the line of the issue, I am
>>> currently blocked in my evaluation of myHDL.
>>>
>>> Thank you in advance.
>>>
>>> Thoma
>>>
<snip>
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 407, in _getNritems
>>>       raise TypeError("Unexpected type")
>>> TypeError: Unexpected type
>

This will be hard to assist with out an example, either the code you are 
trying to convert or a code example.  It possibly looks like an invalid 
type is being converted?

Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

Looks like there is an upfront error check missing,
could you post your code or a simplified version
that exposes the error?

On 05/24/2012 08:43 PM, Thoma HAUC wrote:
> Hi Tom,
>
> I already simulated the design without any issue.
> The exception raises only during verilog generation process.
>
> Thoma
>
>> Not sure but have you simulated it in MyHDL? Usually that will help
>> expose problems better than trying to go directly to Verilog.
>>
>> On 05/21/2012 03:54 PM, Thoma HAUC wrote:
>>> Hi,
>>>
>>> I am new to myHDL and it seems to be a powerful tool.
>>> Today, I need some help to locate the reason of the below exception.
>>> Because there are no clue to indicate the line of the issue, I am
>>> currently blocked in my evaluation of myHDL.
>>>
>>> Thank you in advance.
>>>
>>> Thoma
>>>
>>> Traceback (most recent call last):
>>>     File "bidir_serial.py", line 209, in<module>
>>>       convert2verilog(bidir_serial)
>>>     File "bidir_serial.py", line 200, in convert2verilog
>>>       convert(toVerilog, architecture)
>>>     File "bidir_serial.py", line 194, in convert
>>>       converter(architecture, clr, clk, run, ld, datain, rdy, serialout)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVerilog.py",
>>> line 142, in __call__
>>>       genlist = _analyzeGens(arglist, h.absnames)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 174, in _analyzeGens
>>>       v.visit(tree)
>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>       return visitor(node)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 1078, in visit_Module
>>>       self.generic_visit(node)
>>>     File "/usr/lib/python2.7/ast.py", line 249, in generic_visit
>>>       self.visit(item)
>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>       return visitor(node)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 1154, in visit_FunctionDef
>>>       self.visit(n)
>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>       return visitor(node)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 744, in visit_If
>>>       self.visitList(node.else_)
>>>     File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>>     line
>>> 161, in visitList
>>>       self.visit(n)
>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>       return visitor(node)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 740, in visit_If
>>>       self.visitList(suite)
>>>     File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>>     line
>>> 161, in visitList
>>>       self.visit(n)
>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>       return visitor(node)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 770, in visit_If
>>>       if (len(choices) == _getNritems(var1.obj)) or node.else_:
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 407, in _getNritems
>>>       raise TypeError("Unexpected type")
>>> TypeError: Unexpected type
>
>
> ------------------------------------------------------------------------------
> Live Security Virtual Conference
> Exclusive live event will cover all the ways today's security and
> threat landscape has changed and how IT managers can respond. Discussions
> will include endpoint security, mobile security and the latest in malware
> threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Thoma H. <tho...@gm...>]

Hi Tom,

I already simulated the design without any issue.
The exception raises only during verilog generation process.

Thoma

> Not sure but have you simulated it in MyHDL? Usually that will help
> expose problems better than trying to go directly to Verilog.
> 
> On 05/21/2012 03:54 PM, Thoma HAUC wrote:
>> Hi,
>>
>> I am new to myHDL and it seems to be a powerful tool.
>> Today, I need some help to locate the reason of the below exception.
>> Because there are no clue to indicate the line of the issue, I am
>> currently blocked in my evaluation of myHDL.
>>
>> Thank you in advance.
>>
>> Thoma
>>
>> Traceback (most recent call last):
>>    File "bidir_serial.py", line 209, in<module>
>>      convert2verilog(bidir_serial)
>>    File "bidir_serial.py", line 200, in convert2verilog
>>      convert(toVerilog, architecture)
>>    File "bidir_serial.py", line 194, in convert
>>      converter(architecture, clr, clk, run, ld, datain, rdy, serialout)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVerilog.py",
>> line 142, in __call__
>>      genlist = _analyzeGens(arglist, h.absnames)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 174, in _analyzeGens
>>      v.visit(tree)
>>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>>      return visitor(node)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 1078, in visit_Module
>>      self.generic_visit(node)
>>    File "/usr/lib/python2.7/ast.py", line 249, in generic_visit
>>      self.visit(item)
>>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>>      return visitor(node)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 1154, in visit_FunctionDef
>>      self.visit(n)
>>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>>      return visitor(node)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 744, in visit_If
>>      self.visitList(node.else_)
>>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>    line
>> 161, in visitList
>>      self.visit(n)
>>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>>      return visitor(node)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 740, in visit_If
>>      self.visitList(suite)
>>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>    line
>> 161, in visitList
>>      self.visit(n)
>>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>>      return visitor(node)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 770, in visit_If
>>      if (len(choices) == _getNritems(var1.obj)) or node.else_:
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 407, in _getNritems
>>      raise TypeError("Unexpected type")
>> TypeError: Unexpected type