myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] [PATCH V2] toVHDL: add signal attribute support

[Angel E. <ang...@gm...>]

# HG changeset patch
# User Angel Ezquerra <ang...@gm...>
# Date 1349884148 -7200
# Branch 0.8-dev
# Node ID 6f6571dbd495f197531f0406763ff10e4ce3b3ee
# Parent  58ac2e97c7efbe7e3c9784b8ac25218daa056e40
toVHDL: add signal attribute support

This adds a new setAttribute() method to the Signal type, which lets the user
set attributes that will be set on the VHDL output.

In order to make it easy to avoid declaring the same attribute more than once,
all the signal attributes are written together, after all signal declarations.

The setAttribute() Signal method has the following interface:

    Signal.setAttribute(attribute_name, attribute_value, [attribute_type])

If attribute_type is not set the function will try to guess it (it will be set
to 'string' if the attribute_value is a string, or to integer otherwise).

For example:

    my_signal.setAttribute('test_int_attrib1', 11, 'integer')
    my_signal.setAttribute('test_int_attrib2', -234)
    my_signal.setAttribute('test_string_attrib1', 'test_value1')
    my_signal.setAttribute('test_string_attrib2', 'test_value2', 'string')

Will give the following VHDL output:

    signal my_signal: unsigned(15 downto 0);
    attribute ram_style : string;
    attribute ram_style of my_signal: signal is "block";

    attribute test_int_attrib1 : integer;
    attribute test_int_attrib1 of s_input: signal is 11;
    attribute test_int_attrib2 : integer;
    attribute test_int_attrib2 of s_input: signal is -234;
    attribute test_string_attrib1 : string;
    attribute test_string_attrib1 of s_input: signal is "test_value1";
    attribute test_string_attrib2 : string;
    attribute test_string_attrib2 of s_input: signal is "test_value2";

Currently the attributes are set in alphabetical order. Using a sorted dict to
store the attributes could let us keep their setting order.

An example use case is to be able to tell to the Xilinx XST synthesizer that a
memory must be implemented as Block RAM.

This does not add support for Verilog output.

diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py
--- a/myhdl/_Signal.py
+++ b/myhdl/_Signal.py
@@ -107,10 +107,10 @@
                  '_code', '_tracing', '_nrbits', '_checkVal', 
                  '_setNextVal', '_copyVal2Next', '_printVcd', 
                  '_driven' ,'_read', '_name', '_used', '_inList',
-                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs'
+                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs',
+                 'setAttribute', '_attributes'
                 )
 
-
     def __init__(self, val=None):
         """ Construct a signal.
 
@@ -118,6 +118,7 @@
         
         """
         self._init = deepcopy(val)
+        self._attributes = {}
         self._val = deepcopy(val)
         self._next = deepcopy(val)
         self._min = self._max = None
@@ -300,6 +301,9 @@
     def _printVcdVec(self):
         print >> sim._tf, "b%s %s" % (bin(self._val, self._nrbits), self._code)
 
+    def setAttribute(self, name, value, attribute_type=None):
+        self._attributes[name] = (value, attribute_type)
+
     ### use call interface for shadow signals ###
     def __call__(self, left, right=None):
         s = _SliceSignal(self, left, right)
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -286,6 +286,22 @@
 
 constwires = []
 
+def _writeAttributes(f, siglist):
+    declared_attributes = set()
+    for s in siglist:
+        for name in sorted(s._attributes):
+            value, attribute_type = s._attributes[name]
+            if attribute_type is None:
+                # consider all attributes strings by default
+                attribute_type = 'string'
+                if isinstance(value, int):
+                    attribute_type = 'integer'
+            if name not in declared_attributes:
+                declared_attributes.add(name)
+                print >> f, "    attribute %s : %s;" % (name, attribute_type)
+            if attribute_type == 'string':
+                value = '"%s"' % value
+            print >> f, "    attribute %s of %s: signal is %s;" % (name, s._name, value)
 
 def _writeSigDecls(f, intf, siglist, memlist):
     del constwires[:]
@@ -329,6 +345,9 @@
         t = "t_array_%s" % m.name
         print >> f, "    type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r)
         print >> f, "    signal %s: %s;" % (m.name, t)
+
+    _writeAttributes(f, siglist + memlist)
+
     print >> f
 
 def _writeCompDecls(f,  compDecls):

Re: [myhdl-list] Problems using signal slices and variables

[Angel E. <ang...@gm...>]

On Thu, Oct 11, 2012 at 5:45 PM, Christopher Felton
<chr...@gm...> wrote:
> On 10/11/2012 6:10 AM, Angel Ezquerra wrote:
>> Hi,
>>
>> I'm playing around with concatenating and slicing signals in MyHDL.
>> I'm having some trouble with slicing in particular.
>>
>> I am having a hard time predicting what MyHDL will do when the code is
>> converted to VHDL, and sometimes what I get seems wrong (or at least
>> it is not what I expected).
>>
>> In particular, I've got the following code (note that the code has no
>> purpose other than testing how MyHDL works):
>>
>>      s_input = Signal(intbv(0)[59:])
>>      s_output = Signal(intbv(0)[59:])
>>      s_slice = s_input(15, 0) # Use a shadow signal
>>
>>      @always(clk.posedge, rst.posedge)
>>      def p_process():
>>          if rst == 1:
>>              max_value = s_input.max - 1
>>              s_input.next = max_value
>>              var_test = s_input[15:0] # I expect var_test to be a
>> variable of range 14 downto 0, i.e. size 15
>>              s_output.next = concat(s_input[15:0], s_input[30:15],
>> s_input) # Total size: 15 + 15 + 30 = 60
>>              s_output.next = concat(s_slice, s_input[30:15], s_input)
>> # Total size: 15 + 15 + 30 = 60
>>              s_output.next = concat(var_test, s_input[30:15], s_input)
>> # Total size: 15 + 15 + 30 = 60
>>          else:
>>              pass
>>
>
> Not following your math for the last concat
>
>  >  s_output.next = concat(var_test, s_input[30:15], s_input)
>
>     var_test = 15 (14 downto 0)
>     s_input[30:15] = 15 (29 downto 15 )
>     s_input = 59 (58 downto 0)
>
> trying to concat 89.
>
> In [63]: s_input = Signal(intbv(0)[59:])
>      ...: s_output = Signal(intbv(0)[59:])
>      ...: var_test = s_input[15:0]
>      ...: len(concat(var_test, s_input[30:15], s_input))
>      ...:
> Out[63]: 89
>
> .chris

Sorry Chris,

I made a typo on my example. s_input is 30 bits long, not 60, i.e.

s_input = Signal(intbv(0)[30:])

The problem is that var_test is 30 bits long rather than 15 as I expected.

Cheers,

Angel

Re: [myhdl-list] intbv connections to/from instance array

[Christopher F. <chr...@gm...>]

On 10/11/2012 8:39 AM, Michael Babst wrote:
> Thanks a lot, Chris, that works!
>
> Yes, I already fell into the trap of trying using lists at the top
> level.  I was hoping to use it to
> model an array of N std_logic_vectors in VHDL.
>
> That led me to this simpler bit array <-> intbv problem.  Based on
> your solution, I created
> two simple functions to make the connections: intvb2bool and
> bool2intbv.  The program
> is attached.  It is a little unsatisfying to have so much code for a
> wire, but I suspect
> that's why the shadow_signals were created.
>
> I appreciate the help with my noob questions as I become more familiar with the
> nuances of this cool tool.
>
> Mike
>
>

Not sure why the shadow signals didn't work.  I haven't
used shadow signals much.  I will experiment with them
some more and see if I can get it working or if there
is a bug.

Regards,
Chris

Re: [myhdl-list] Problems using signal slices and variables

[Christopher F. <chr...@gm...>]

On 10/11/2012 6:10 AM, Angel Ezquerra wrote:
> Hi,
>
> I'm playing around with concatenating and slicing signals in MyHDL.
> I'm having some trouble with slicing in particular.
>
> I am having a hard time predicting what MyHDL will do when the code is
> converted to VHDL, and sometimes what I get seems wrong (or at least
> it is not what I expected).
>
> In particular, I've got the following code (note that the code has no
> purpose other than testing how MyHDL works):
>
>      s_input = Signal(intbv(0)[59:])
>      s_output = Signal(intbv(0)[59:])
>      s_slice = s_input(15, 0) # Use a shadow signal
>
>      @always(clk.posedge, rst.posedge)
>      def p_process():
>          if rst == 1:
>              max_value = s_input.max - 1
>              s_input.next = max_value
>              var_test = s_input[15:0] # I expect var_test to be a
> variable of range 14 downto 0, i.e. size 15
>              s_output.next = concat(s_input[15:0], s_input[30:15],
> s_input) # Total size: 15 + 15 + 30 = 60
>              s_output.next = concat(s_slice, s_input[30:15], s_input)
> # Total size: 15 + 15 + 30 = 60
>              s_output.next = concat(var_test, s_input[30:15], s_input)
> # Total size: 15 + 15 + 30 = 60
>          else:
>              pass
>

Not following your math for the last concat

 >  s_output.next = concat(var_test, s_input[30:15], s_input)

    var_test = 15 (14 downto 0)
    s_input[30:15] = 15 (29 downto 15 )
    s_input = 59 (58 downto 0)

trying to concat 89.

In [63]: s_input = Signal(intbv(0)[59:])
     ...: s_output = Signal(intbv(0)[59:])
     ...: var_test = s_input[15:0]
     ...: len(concat(var_test, s_input[30:15], s_input))
     ...:
Out[63]: 89

.chris

Re: [myhdl-list] Problems converting an integer assignment into VHDL

[Christopher F. <chr...@gm...>]

On 10/11/2012 9:52 AM, Christopher Felton wrote:
> <snip>
>>
>>
>> so it turns out that the converter doesn't recognise the "s_my_signal.max"
>> as an const integer, but instead as a signal.
>> This seems to be also the case for the simulator.
>> e.g:  In a combinatorical process this leads to a -> combinatorical loop
>> error, when there is actually none.
>>
>>
>>        sigTest=Signal(intbv(0)[4:])
>>        @always_comb
>>        def comb_setConst():
>>          sigTest.next=int(sigTest.max)-1
>>
>>
>
> Yes, in a generator an "buried" constant can't be used.
> The converter will not walk down the structure (list,
> dict, class, etc) to find the value.  On the right hand
> side the only valid types are for conversion:
>
>       int, long, intbv, bool
>

I didn't mention the special case of tuple of ints and
list of signals.  These two cases a structure can be
used on the right hand side.

.chris

Re: [myhdl-list] Problems converting an integer assignment into VHDL

[Christopher F. <chr...@gm...>]

<snip>
>
>
> so it turns out that the converter doesn't recognise the "s_my_signal.max"
> as an const integer, but instead as a signal.
> This seems to be also the case for the simulator.
> e.g:  In a combinatorical process this leads to a -> combinatorical loop
> error, when there is actually none.
>
>
>       sigTest=Signal(intbv(0)[4:])
>       @always_comb
>       def comb_setConst():
>         sigTest.next=int(sigTest.max)-1
>
>

Yes, in a generator an "buried" constant can't be used.
The converter will not walk down the structure (list,
dict, class, etc) to find the value.  On the right hand
side the only valid types are for conversion:

     int, long, intbv, bool

A Signal can also be on the right hand side as lot as
the Signal contains one of the above types.


Another method vs. converting to an int would be

    Max = sigTest.max
    @always_comb
    def com_setConst():
        sigTest.next = Max-1


The error that occurred in simulation is slightly different.
Because you could use the above in an @always decorator and
in simulation it will work but it will not convert.  The
in / out is to protect from infinite recursive delta cycles.

    @always_comb
    def hdl():
         sigTest.next = not sigTest

Regards,
Chris

Re: [myhdl-list] intbv connections to/from instance array

[Michael B. <ms...@gm...>]

Thanks a lot, Chris, that works!

Yes, I already fell into the trap of trying using lists at the top
level.  I was hoping to use it to
model an array of N std_logic_vectors in VHDL.

That led me to this simpler bit array <-> intbv problem.  Based on
your solution, I created
two simple functions to make the connections: intvb2bool and
bool2intbv.  The program
is attached.  It is a little unsatisfying to have so much code for a
wire, but I suspect
that's why the shadow_signals were created.

I appreciate the help with my noob questions as I become more familiar with the
nuances of this cool tool.

Mike


On Wed, Oct 10, 2012 at 3:59 PM, Christopher Felton
<chr...@gm...> wrote:
> On 10/10/2012 12:07 PM, Michael Babst wrote:
>> What is the preferred method to connect the intbv signals to/from
>> an instance array.  In the example code below, the connections to
>> dvec and qvec are not made in the generated VHDL.  I have been
>> unable to get shadow signals or signal lists to work in this
>> scenario.
>>
>> Thank you!
>>
>>
>> from myhdl import *
>>
>> N = 8
>>
>> def reg(d,q,en,clk,arstn):
>>      @always(clk.posedge, arstn.negedge)
>>      def regLogic():
>>          if arstn == 0:
>>              q.next = 0
>>          else:
>>              if en:
>>                  q.next = d
>>      return regLogic
>>
>>
>> def regArray(dvec,qvec,en,clk,arstn):
>>
>>      u_reg = [None for i in range(N)]
>>
>>      for i in range(N):
>>          u_reg[i]     = reg(dvec[i],qvec[i],en,clk,arstn)
>>
>>      return u_reg
>>
>>
>> en         = Signal(bool(0))
>> clk, arstn = [Signal(bool()) for i in range(2)]
>>
>> dvec       = Signal(intbv(0)[N:])
>> qvec       = Signal(intbv(0)[N:])
>>
>> toVHDL(regArray,dvec,qvec,en,clk,arstn)
>>
>
>
> Hmmm, I had some difficulty getting the shadow signal
> method to work, as well.  The following is my list-of-signals
> (LoS) version.  The LoS can only be used locally, can't
> be passed as a top-level port.
>
> In [49]: from myhdl import *
>      ...:
>      ...: N = 8
>      ...:
>      ...: def reg(d,q,en,clk,arstn):
>      ...:     @always(clk.posedge, arstn.negedge)
>      ...:     def regLogic():
>      ...:         if arstn == 0:
>      ...:             q.next = 0
>      ...:         else:
>      ...:             if en:
>      ...:                 q.next = d
>      ...:     return regLogic
>      ...:
>      ...:
>      ...: def regArray(dvec,qvec,en,clk,arstn):
>      ...:
>      ...:     u_reg = [None for i in range(N)]
>      ...:     d = [Signal(bool(0)) for ii in range(N)]
>      ...:     q = [Signal(bool(0)) for ii in range(N)]
>      ...:
>      ...:     @always_comb
>      ...:     def hdl_assigns():
>      ...:         for jj in range(N):
>      ...:             d[jj].next = dvec[jj]
>      ...:             qvec.next[jj] = q[jj]
>      ...:
>      ...:     for i in range(N):
>      ...:         u_reg[i] = reg(d[i],q[i],en,clk,arstn)
>      ...:
>      ...:     return hdl_assigns, u_reg
>      ...:
>      ...:
>      ...: en         = Signal(bool(0))
>      ...: clk, arstn = [Signal(bool()) for i in range(2)]
>      ...:
>      ...: dvec       = Signal(intbv(0)[N:])
>      ...: qvec       = Signal(intbv(0)[N:])
>      ...:
>      ...: toVHDL(regArray,dvec,qvec,en,clk,arstn)
>
>
> Manual reference is here:
> http://www.myhdl.org/doc/0.7/manual/modeling.html#inferring-the-list-of-instances
>
> Regards,
> Chris
>
>
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>
>
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Re: [myhdl-list] Problems converting an integer assignment into VHDL

[Angel E. <ang...@gm...>]

Benoit,

thank you for your comment. I think your advice is sensible. However I
have two purposes with this:

1. Learn the nits of the language. What can be done and what cannot be done
2. See how I can use MyHDL on a project that already uses VHDL

#1 is the reason why I am trying to convert an existing module. I know
what it must do so it is easy to try the current behavior. I purposely
tried to directly translate it, rather than coding it from scratch
just to see what VHDL constructs translate well to MyHDL and which do
not. I hope this will also teach which constructs are synthesizable
and which are not. My intention is to rewrite it again from scratch
once this intial learning phase is done.

Most importantly however, purpose #2 places several fundamental
limitations on how I can use the language. In particular I am bound to
use the interfaces that are provided to me by the rest of the modules
on our project, most of which I cannot control.

All our interfaces use std_logic_vectors and often these
std_logic_vectors group several fields (which are simply
concatenated). This is often quite low level (which I guess is common
when writing synthesizable VHDL code) and  forces me to work with and
"think in bits" even if that is not the natural level of abstraction
of MyHDL.

For example our current interfaces sometimes use the "all 1" value to
indicate that some data is invalid. My first approach to this in MyHDL
was to "forget about the bits" and set the value of that signal using
its max property (minus 1). However this does not work that well (as
discussed on another thread). This is exactly the kind of thing I am
trying to discover.

I think it would be much easier to follow your advice if I were to use
MyHDL on a project that were started from scratch. But unfortunately
that is not the case :-(

Cheers,

Angel


On Thu, Oct 11, 2012 at 1:48 PM, Ben <ben...@gm...> wrote:
> On Thu, Oct 11, 2012 at 12:06 PM, Angel Ezquerra
> <ang...@gm...> wrote:
>> That being said, is this technique to set a signal to all '1' the one
>> you guys would use? Or is there a more idiomatic way?
>>
>
> With all my respect, you are looking at it the wrong way.
>
> I know you are trying to 'translate' a module from VHDL to MyHDL, but
> you should understand that both language are far from being
> 'equivalent'. With MyHDL, you are climbing in the abstraction, and
> trying to write your MyHDL so that it looks like the VHDL can only
> produce poor code.
>
> Try to take some time, and think of the functionality of your module
> again, do that the MyHDL way, with all the power of Python, you could
> get some nice surprises. Your code should become simpler.
>
> I understand it's difficult at first to completely grasp the power of
> the tool you have at hand. You saw it running, it has some nice
> features, but where do they end ? I saw lately some nice examples with
> the signal containers for instance, especially the one that did not
> necessitate any modification of the MyHDL source code, support for it
> is there, simply because it's python.
>
> Your value of 111....111, what is it ? an invalid state ? an
> uninitialised state ? a valid one? Each of those answer has it's own
> way to write it. You should step up and forget about the 1 and the 0
> ...
>
> Hope this helps.
>
> Have fun coding !
> Benoît.

Re: [myhdl-list] Problems converting an integer assignment into VHDL

[Ben <ben...@gm...>]

On Thu, Oct 11, 2012 at 12:06 PM, Angel Ezquerra
<ang...@gm...> wrote:
> That being said, is this technique to set a signal to all '1' the one
> you guys would use? Or is there a more idiomatic way?
>

With all my respect, you are looking at it the wrong way.

I know you are trying to 'translate' a module from VHDL to MyHDL, but
you should understand that both language are far from being
'equivalent'. With MyHDL, you are climbing in the abstraction, and
trying to write your MyHDL so that it looks like the VHDL can only
produce poor code.

Try to take some time, and think of the functionality of your module
again, do that the MyHDL way, with all the power of Python, you could
get some nice surprises. Your code should become simpler.

I understand it's difficult at first to completely grasp the power of
the tool you have at hand. You saw it running, it has some nice
features, but where do they end ? I saw lately some nice examples with
the signal containers for instance, especially the one that did not
necessitate any modification of the MyHDL source code, support for it
is there, simply because it's python.

Your value of 111....111, what is it ? an invalid state ? an
uninitialised state ? a valid one? Each of those answer has it's own
way to write it. You should step up and forget about the 1 and the 0
...

Hope this helps.

Have fun coding !
Benoît.

[myhdl-list] Problems using signal slices and variables

[Angel E. <ang...@gm...>]

Hi,

I'm playing around with concatenating and slicing signals in MyHDL.
I'm having some trouble with slicing in particular.

I am having a hard time predicting what MyHDL will do when the code is
converted to VHDL, and sometimes what I get seems wrong (or at least
it is not what I expected).

In particular, I've got the following code (note that the code has no
purpose other than testing how MyHDL works):

    s_input = Signal(intbv(0)[59:])
    s_output = Signal(intbv(0)[59:])
    s_slice = s_input(15, 0) # Use a shadow signal

    @always(clk.posedge, rst.posedge)
    def p_process():
        if rst == 1:
            max_value = s_input.max - 1
            s_input.next = max_value
            var_test = s_input[15:0] # I expect var_test to be a
variable of range 14 downto 0, i.e. size 15
            s_output.next = concat(s_input[15:0], s_input[30:15],
s_input) # Total size: 15 + 15 + 30 = 60
            s_output.next = concat(s_slice, s_input[30:15], s_input)
# Total size: 15 + 15 + 30 = 60
            s_output.next = concat(var_test, s_input[30:15], s_input)
# Total size: 15 + 15 + 30 = 60
        else:
            pass

And I get:

TEST_MODULE_P_PROCESS: process (clk, rst) is
    variable max_value: integer;
    variable var_test: unsigned(29 downto 0);
begin
    if (rst = '1') then
        max_value := to_integer(1073741824 - 1);
        s_input <= to_unsigned(max_value, 30);
        var_test := resize(s_input(15-1 downto 0), 30);
        s_output <= unsigned'(s_input(15-1 downto 0) & s_input(30-1
downto 15) & s_input);
        s_output <= unsigned'(s_input(15-1 downto 0) & s_input(30-1
downto 15) & s_input);
        s_output <= unsigned'(var_test & s_input(30-1 downto 15) & s_input);
    elsif rising_edge(clk) then
        null;
    end if;
end process TEST_MODULE_P_PROCESS;

What I do not understand is why MyHDL makes var_test be of size 30,
which results in it using resize and then makes the last statement:

        s_output <= unsigned'(var_test & s_input(30-1 downto 15) & s_input);

appear to be wrong, since s_output has size 60, while var_test and
s_input have size 30. The total size above would be 30 + 15 + 30, i.e.
75.

I am getting this wrong?

Thanks,

Angel

Re: [myhdl-list] Problems converting an integer assignment into VHDL

[Angel E. <ang...@gm...>]

Thank you Norbo.

My comments below.

On Thu, Oct 11, 2012 at 11:24 AM, Norbo <Nor...@gm...> wrote:
> Am 11.10.2012, 10:31 Uhr, schrieb Angel Ezquerra
> <ang...@gm...>:
>
>> Hi,
>>
>> I got an issue with conversion to VHDL, where MyHDL seems to do the
>> wrong thing (although most likely it's me who is doing it wrong).
>>
>> The problem is that MyHDL maps an integer assignment into an intbv
>> signal as a direct integer assignment in VHDL, instead of using a
>> to_unsigned conversion.
>>
>> That is, I got a signal declared as follows:
>>
>>     signal s_my_signal: unsigned(29 downto 0);
>>
>> Then I do:
>>
>>     s_my_signal.next = s_my_signal.max - 1
>>
>> which in VHDL becomes:
>>
>>     s_my_signal.next <= 1073741824 - 1;
>>
>> Which is wrong. Instead I expected it to be:
>>
>>     s_my_signal.next <= to_unsigned(1073741824 - 1, 30);
>>
>
> Yup that causes problems. which is funny because if you write in the myhdl
> code:
>
> s_my_signal.next <= 1073741824 - 1;
>
> the result is:
>
> s_my_signal <= to_unsigned(1073741824 - 1, 30);
>
> or if you write:
>
> CONST_MAX=s_my_signal.max
> @always(clk.posedge)
> def ttt():
>     s_my_signal.next <= CONST_MAX - 1;
>
>
> which converts to:
>
> s_my_signal <= to_unsigned(1073741824 - 1, 30);
>
>
> if you write:
>
> s_my_signal.next = int(s_my_signal.max) - 1
>
> it converts to:
>
> s_my_signal <= to_unsigned(1073741824 - 1, 30);
>
>
>
> or if you write:
>
> s_my_signal.next = intbv(s_my_signal.max) - 1
>
> it converts to:
>
> s_my_signal <= to_unsigned(1073741824 - 1, 30);


The problem is even easier to run into, since the convertor fails if
you do not add anything.

This:

    s_2pps_counter.next = int(s_2pps_counter.min)

Converts into:

    s_2pps_counter <= 0;

Which is wrong, while this:

    s_2pps_counter.next = int(s_2pps_counter.min) + 0

Converts into:

    s_2pps_counter <= to_unsigned(0 + 0, 30);

Which is correct.

Another failure is that this:

    s_2pps_counter.next = int(s_2pps_counter.min) + 0

Converts into:

    s_2pps_counter <= to_integer(0 + 0);

Which is also wrong. So you cannot just use "int" to make sure that
.min and .max are properly interpreted.


> so it turns out that the converter doesn't recognise the "s_my_signal.max"
> as an const integer, but instead as a signal.
> This seems to be also the case for the simulator.

That seems to be the problem indeed.

> e.g:  In a combinatorical process this leads to a -> combinatorical loop
> error, when there is actually none.
>
>
>      sigTest=Signal(intbv(0)[4:])
>      @always_comb
>      def comb_setConst():
>        sigTest.next=int(sigTest.max)-1
>
>
> leads to the error message:
>
> --myhdl.AlwaysCombError: signal (sigTest) used as inout in always_comb
> function argument
>
>
>
> but it could be written like this:
>
>      sigTest=Signal(intbv(0)[4:])
>      maxvalue=sigTest.max
>      @always_comb
>      def comb_setConst():
>        sigTest.next=maxvalue-1
>
> this would make the simulator core happy and would be fine if the
> sensitivity list is not empty!!

Yes, it seems that using an intermediate variable to get the value of
s_my_signal.max works fine and is an easy work around.

That being said, is this technique to set a signal to all '1' the one
you guys would use? Or is there a more idiomatic way?

Cheers,

Angel

Re: [myhdl-list] Problems converting an integer assignment into VHDL

[Norbo <Nor...@gm...>]

Am 11.10.2012, 10:31 Uhr, schrieb Angel Ezquerra  
<ang...@gm...>:

> Hi,
>
> I got an issue with conversion to VHDL, where MyHDL seems to do the
> wrong thing (although most likely it's me who is doing it wrong).
>
> The problem is that MyHDL maps an integer assignment into an intbv
> signal as a direct integer assignment in VHDL, instead of using a
> to_unsigned conversion.
>
> That is, I got a signal declared as follows:
>
>     signal s_my_signal: unsigned(29 downto 0);
>
> Then I do:
>
>     s_my_signal.next = s_my_signal.max - 1
>
> which in VHDL becomes:
>
>     s_my_signal.next <= 1073741824 - 1;
>
> Which is wrong. Instead I expected it to be:
>
>     s_my_signal.next <= to_unsigned(1073741824 - 1, 30);
>

Yup that causes problems. which is funny because if you write in the myhdl  
code:

s_my_signal.next <= 1073741824 - 1;

the result is:

s_my_signal <= to_unsigned(1073741824 - 1, 30);

or if you write:

CONST_MAX=s_my_signal.max
@always(clk.posedge)
def ttt():
    s_my_signal.next <= CONST_MAX - 1;


which converts to:

s_my_signal <= to_unsigned(1073741824 - 1, 30);


if you write:

s_my_signal.next = int(s_my_signal.max) - 1

it converts to:

s_my_signal <= to_unsigned(1073741824 - 1, 30);



or if you write:

s_my_signal.next = intbv(s_my_signal.max) - 1

it converts to:

s_my_signal <= to_unsigned(1073741824 - 1, 30);




so it turns out that the converter doesn't recognise the "s_my_signal.max"  
as an const integer, but instead as a signal.
This seems to be also the case for the simulator.
e.g:  In a combinatorical process this leads to a -> combinatorical loop  
error, when there is actually none.


     sigTest=Signal(intbv(0)[4:])
     @always_comb
     def comb_setConst():
       sigTest.next=int(sigTest.max)-1


leads to the error message:

--myhdl.AlwaysCombError: signal (sigTest) used as inout in always_comb  
function argument



but it could be written like this:

     sigTest=Signal(intbv(0)[4:])
     maxvalue=sigTest.max
     @always_comb
     def comb_setConst():
       sigTest.next=maxvalue-1

this would make the simulator core happy and would be fine if the  
sensitivity list is not empty!!


greetings
Norbert

Re: [myhdl-list] [PATCH RFC] toVHDL: add signal attribute support

[Angel E. <ang...@gm...>]

I just realized that this patch is wrong, as it doesn't add a ";"
after the statement that sets the attribute.

I'll resend a new version of this patch shortly.

Cheers,

Angel


On Wed, Oct 10, 2012 at 5:53 PM, Angel Ezquerra
<ang...@gm...> wrote:
> This patch is unrelated to the ones I sent before and it will probably
> be more controversial. That is why I marked it as RFC, i.e. Request
> For Comments, as is often done in other mailing lists.
>
> It adds a way to add signal attributes to the VHDL code. I tried to
> follow the style of the rest of the code but I am sure there are
> things that I could have done differently.
>
> Comments are welcome.
>
> Cheers,
>
> Angel
>
>
> On Wed, Oct 10, 2012 at 5:49 PM, Angel Ezquerra
> <ang...@gm...> wrote:
>> # HG changeset patch
>> # User Angel Ezquerra <ang...@gm...>
>> # Date 1349884148 -7200
>> # Branch 0.8-dev
>> # Node ID cdd0b98bc565ce08c5ab47417551e7719313d9ce
>> # Parent  58ac2e97c7efbe7e3c9784b8ac25218daa056e40
>> toVHDL: add signal attribute support
>>
>> This adds a new setAttribute() method to the Signal type, which lets the user
>> set attributes that will be set on the VHDL output.
>>
>> In order to make it easy to avoid declaring the same attribute more than once,
>> all the signal attributes are written toguether, after all signal declarations.
>>
>> The setAttribute() Signal method has the following interface:
>>
>>     Signal.setAttribute(attribute_name, attribute_value, [attribute_type])
>>
>> If attribute_type is not set it will default to string.
>>
>> diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py
>> --- a/myhdl/_Signal.py
>> +++ b/myhdl/_Signal.py
>> @@ -107,10 +107,10 @@
>>                   '_code', '_tracing', '_nrbits', '_checkVal',
>>                   '_setNextVal', '_copyVal2Next', '_printVcd',
>>                   '_driven' ,'_read', '_name', '_used', '_inList',
>> -                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs'
>> +                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs',
>> +                 'setAttribute', '_attributes'
>>                  )
>>
>> -
>>      def __init__(self, val=None):
>>          """ Construct a signal.
>>
>> @@ -118,6 +118,7 @@
>>
>>          """
>>          self._init = deepcopy(val)
>> +        self._attributes = {}
>>          self._val = deepcopy(val)
>>          self._next = deepcopy(val)
>>          self._min = self._max = None
>> @@ -300,6 +301,9 @@
>>      def _printVcdVec(self):
>>          print >> sim._tf, "b%s %s" % (bin(self._val, self._nrbits), self._code)
>>
>> +    def setAttribute(self, name, value, attribute_type=None):
>> +        self._attributes[name] = (value, attribute_type)
>> +
>>      ### use call interface for shadow signals ###
>>      def __call__(self, left, right=None):
>>          s = _SliceSignal(self, left, right)
>> diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
>> --- a/myhdl/conversion/_toVHDL.py
>> +++ b/myhdl/conversion/_toVHDL.py
>> @@ -286,6 +286,22 @@
>>
>>  constwires = []
>>
>> +def _writeAttributes(f, siglist):
>> +    declared_attributes = set()
>> +    for s in siglist:
>> +        for name in s._attributes:
>> +            value, attribute_type = s._attributes[name]
>> +            if attribute_type is None:
>> +                # consider all attributes strings by default
>> +                attribute_type = 'string'
>> +                if isinstance(value, int):
>> +                    attribute_type = 'integer'
>> +            if name not in declared_attributes:
>> +                declared_attributes.add(name)
>> +                print >> f, "    attribute %s : %s;" % (name, attribute_type)
>> +
>> +                value = '"%s"' % value
>> +            print >> f, "    attribute %s of %s: signal is %s" % (name, s._name, value)
>>
>>  def _writeSigDecls(f, intf, siglist, memlist):
>>      del constwires[:]
>> @@ -329,6 +345,9 @@
>>          t = "t_array_%s" % m.name
>>          print >> f, "    type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r)
>>          print >> f, "    signal %s: %s;" % (m.name, t)
>> +
>> +    _writeAttributes(f, siglist + memlist)
>> +
>>      print >> f
>>
>>  def _writeCompDecls(f,  compDecls):
>>
>> ------------------------------------------------------------------------------
>> Don't let slow site performance ruin your business. Deploy New Relic APM
>> Deploy New Relic app performance management and know exactly
>> what is happening inside your Ruby, Python, PHP, Java, and .NET app
>> Try New Relic at no cost today and get our sweet Data Nerd shirt too!
>> http://p.sf.net/sfu/newrelic-dev2dev
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>

[myhdl-list] Problems converting an integer assignment into VHDL

[Angel E. <ang...@gm...>]

Hi,

I got an issue with conversion to VHDL, where MyHDL seems to do the
wrong thing (although most likely it's me who is doing it wrong).

The problem is that MyHDL maps an integer assignment into an intbv
signal as a direct integer assignment in VHDL, instead of using a
to_unsigned conversion.

That is, I got a signal declared as follows:

    signal s_my_signal: unsigned(29 downto 0);

Then I do:

    s_my_signal.next = s_my_signal.max - 1

which in VHDL becomes:

    s_my_signal.next <= 1073741824 - 1;

Which is wrong. Instead I expected it to be:

    s_my_signal.next <= to_unsigned(1073741824 - 1, 30);

Or something of the sort.

I thought that I could fix the problem by doing:

    s_my_signal.next = intbv(1073741824.max)[len(s_2pps_counter):]

Which would be unnecessarily verbose (IMHO) but in fact it makes
matters worse, as it converts into:

    s_2pps_counter <= 1073741824(30-1 downto 0);

Is there something I'm doing wrong?

Additionally, is this the best way to initialize an unsigned signal to
all 1's? This is probably not in the "MyHDL style" but for now I'm
just trying to convert an existing VHDL module into MyHDL just to get
the feel of things.

Thanks,

Angel

Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Angel E. <ezq...@gm...>]

On Oct 10, 2012 10:05 PM, "Christopher Felton" <chr...@gm...>
wrote:
>
> <snip>
> >
> > I was able to run the VHDL conversion tests, but I got 5 passes and 40
> > failures _without_ my patches. With my patches I get the same result.
> > This is the output of running py.test on the
> > myhdl\test\conversion\toVHDL folder:
> >
> > $ /c/Python27/Scripts/py.test
> > ============================= test session starts
==============================
> > platform win32 -- Python 2.7.2 -- pytest-2.2.4
> > collecting ... collected 45 items
> >
> > test_custom.py FFFF..
> > test_enum.py F
> > test_loops.py .
> > test_newcustom.py FFFF..
> > test_ops.py FFFFFFFFFFFFFF
> > test_signed.py FFFFFFFFFFFFFFFFF
> >
> > =================================== FAILURES
===================================
>
> I haven't run the VHDL conversion tests on WIN32.  Do you
> have GHDL installed?
>
> .chris

Yes, and it is in the path (if I run ghdl from the command prompt it finds
it).

Angel

Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Christopher F. <chr...@gm...>]

<snip>
>
> I was able to run the VHDL conversion tests, but I got 5 passes and 40
> failures _without_ my patches. With my patches I get the same result.
> This is the output of running py.test on the
> myhdl\test\conversion\toVHDL folder:
>
> $ /c/Python27/Scripts/py.test
> ============================= test session starts ==============================
> platform win32 -- Python 2.7.2 -- pytest-2.2.4
> collecting ... collected 45 items
>
> test_custom.py FFFF..
> test_enum.py F
> test_loops.py .
> test_newcustom.py FFFF..
> test_ops.py FFFFFFFFFFFFFF
> test_signed.py FFFFFFFFFFFFFFFFF
>
> =================================== FAILURES ===================================

I haven't run the VHDL conversion tests on WIN32.  Do you
have GHDL installed?

.chris

Re: [myhdl-list] intbv connections to/from instance array

[Christopher F. <chr...@gm...>]

On 10/10/2012 12:07 PM, Michael Babst wrote:
> What is the preferred method to connect the intbv signals to/from
> an instance array.  In the example code below, the connections to
> dvec and qvec are not made in the generated VHDL.  I have been
> unable to get shadow signals or signal lists to work in this
> scenario.
>
> Thank you!
>
>
> from myhdl import *
>
> N = 8
>
> def reg(d,q,en,clk,arstn):
>      @always(clk.posedge, arstn.negedge)
>      def regLogic():
>          if arstn == 0:
>              q.next = 0
>          else:
>              if en:
>                  q.next = d
>      return regLogic
>
>
> def regArray(dvec,qvec,en,clk,arstn):
>
>      u_reg = [None for i in range(N)]
>
>      for i in range(N):
>          u_reg[i]     = reg(dvec[i],qvec[i],en,clk,arstn)
>
>      return u_reg
>
>
> en         = Signal(bool(0))
> clk, arstn = [Signal(bool()) for i in range(2)]
>
> dvec       = Signal(intbv(0)[N:])
> qvec       = Signal(intbv(0)[N:])
>
> toVHDL(regArray,dvec,qvec,en,clk,arstn)
>


Hmmm, I had some difficulty getting the shadow signal
method to work, as well.  The following is my list-of-signals
(LoS) version.  The LoS can only be used locally, can't
be passed as a top-level port.

In [49]: from myhdl import *
     ...:
     ...: N = 8
     ...:
     ...: def reg(d,q,en,clk,arstn):
     ...:     @always(clk.posedge, arstn.negedge)
     ...:     def regLogic():
     ...:         if arstn == 0:
     ...:             q.next = 0
     ...:         else:
     ...:             if en:
     ...:                 q.next = d
     ...:     return regLogic
     ...:
     ...:
     ...: def regArray(dvec,qvec,en,clk,arstn):
     ...:
     ...:     u_reg = [None for i in range(N)]
     ...:     d = [Signal(bool(0)) for ii in range(N)]
     ...:     q = [Signal(bool(0)) for ii in range(N)]
     ...:
     ...:     @always_comb
     ...:     def hdl_assigns():
     ...:         for jj in range(N):
     ...:             d[jj].next = dvec[jj]
     ...:             qvec.next[jj] = q[jj]
     ...:
     ...:     for i in range(N):
     ...:         u_reg[i] = reg(d[i],q[i],en,clk,arstn)
     ...:
     ...:     return hdl_assigns, u_reg
     ...:
     ...:
     ...: en         = Signal(bool(0))
     ...: clk, arstn = [Signal(bool()) for i in range(2)]
     ...:
     ...: dvec       = Signal(intbv(0)[N:])
     ...: qvec       = Signal(intbv(0)[N:])
     ...:
     ...: toVHDL(regArray,dvec,qvec,en,clk,arstn)


Manual reference is here:
http://www.myhdl.org/doc/0.7/manual/modeling.html#inferring-the-list-of-instances

Regards,
Chris


> ------------------------------------------------------------------------------
> Don't let slow site performance ruin your business. Deploy New Relic APM
> Deploy New Relic app performance management and know exactly
> what is happening inside your Ruby, Python, PHP, Java, and .NET app
> Try New Relic at no cost today and get our sweet Data Nerd shirt too!
> http://p.sf.net/sfu/newrelic-dev2dev
>

[myhdl-list] intbv connections to/from instance array

[Michael B. <ms...@gm...>]

What is the preferred method to connect the intbv signals to/from
an instance array.  In the example code below, the connections to
dvec and qvec are not made in the generated VHDL.  I have been
unable to get shadow signals or signal lists to work in this
scenario.

Thank you!


from myhdl import *

N = 8

def reg(d,q,en,clk,arstn):
    @always(clk.posedge, arstn.negedge)
    def regLogic():
        if arstn == 0:
            q.next = 0
        else:
            if en:
                q.next = d
    return regLogic


def regArray(dvec,qvec,en,clk,arstn):

    u_reg = [None for i in range(N)]

    for i in range(N):
        u_reg[i]     = reg(dvec[i],qvec[i],en,clk,arstn)

    return u_reg


en         = Signal(bool(0))
clk, arstn = [Signal(bool()) for i in range(2)]

dvec       = Signal(intbv(0)[N:])
qvec       = Signal(intbv(0)[N:])

toVHDL(regArray,dvec,qvec,en,clk,arstn)

Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Angel E. <ang...@gm...>]

On Wed, Oct 10, 2012 at 6:09 PM, Christopher Felton
<chr...@gm...> wrote:
> On 10/10/2012 11:04 AM, Angel Ezquerra wrote:
>> On Wed, Oct 10, 2012 at 5:56 PM, Christopher Felton
>> <chr...@gm...> wrote:
>>> On 10/10/2012 10:46 AM, Angel Ezquerra wrote:
>>>> On Wed, Oct 10, 2012 at 2:25 PM, Christopher Felton
>>>> <chr...@gm...> wrote:
>>>>> <snip>
>>>>>>
>>>>>>
>>>>>>>> Anyway, since this process seems easy to automate (I can't really
>>>>>>>> tell, since I don't really understand it), the obvious question is why
>>>>>>>> not make MyHDL itself automate it for us? That should put to rest the
>>>>>>>> question of generating hierarchical VHDL or Verilog code which seems
>>>>>>>> to crop up regularly on this list and on other online discussions
>>>>>>>> about MyHDL!
>>>>>>>
>>>>>>> The obvious question is why someone interested in a
>>>>>>> feature doesn't propose a MEP and a patch?
>>>>>>
>>>>>> That is a fair point. I am still "testing the waters" with MyHDL so to
>>>>>> speak, so for now I am just raising the concerns that I come up with.
>>>>>>
>>>>>> I could try to write a MEP but first I'd like to see if there is some
>>>>>> consensus that this could be a worthy idea (as I believe it is). Also,
>>>>>> what would be the preferred way to indicate that a group of generators
>>>>>> should be grouped into an entity and placed on their own file?
>>>>>>
>>>>>> For example, in the case that you described, imagine that you had had
>>>>>> a magic wand that let you modify MyHDL in a way that you could have
>>>>>> avoided all the manual work involved in solving your problem. How
>>>>>> would you have liked to be able to tell MyHDL that you wanted to place
>>>>>> "submodule" on its own file?
>>>>>>
>>>>>> Contributing a patch is another matter though. I am quite busy
>>>>>> contributing to TortoiseHg at the moment and I don't know how complex
>>>>>> the MyHDL code base is. I don't know that I'd have the time to dig
>>>>>> deep enough into it to contribute such a patch.
>>>>>>
>>>>>
>>>>> I am having a hard time following you.  At one point
>>>>> you comment
>>>>>
>>>>>       "since this process seems easy to automate ..."
>>>>>
>>>>> then you comment
>>>>>
>>>>>       "... the amount of steps would be great"
>>>>>       (implying difficulty)
>>>>>
>>>>> But if it is easy to automate why would we be concerned
>>>>> with the number of steps?
>>>>
>>>> I should have been more clear:
>>>> - The process "seems easy to automate" according to what you said.
>>>> - But it _currently_ requires a great number of steps since it must be
>>>> performed _manually_ (which does not necessarily mean that it would be
>>>> hard, just tiresome).
>>>>
>>>> That is, currently MyHDL does not provide a way to make this without
>>>> too much effort, but apparently (from what you said) it should be
>>>> possible to make it automatic.
>>>>
>>>>> I also get confused if you are only interested in an
>>>>> existing solution or you are willing to experiment and
>>>>> be part of a development.  This conversation seems to
>>>>> bounce back and forth between wanting a working solution
>>>>> and "testing the waters".  I am never sure which I am
>>>>> replying to.  Given the comments above, I assume you
>>>>> are mainly interested in existing and working solutions.
>>>>>
>>>>> Maintaining hierarchy during conversion is a reasonable
>>>>> feature request.  But the priority of the feature?  And
>>>>> the best path forward?  I think it is safe to say, given
>>>>> the resources available this feature will not be added
>>>>> any time soon.  I think you are simply trying to stimulate
>>>>> conversation and ideas (which is good!).  But I don't believe
>>>>> anyone has the bandwidth to experiment and implement the
>>>>> feature.
>>>>
>>>> I'm mostly interested on working solutions, but since it seems there
>>>> are none (at least not experimental ones), I want to spur the
>>>> conversation some and show that there are people (at least one! :-)
>>>> interested on this feature.
>>>>
>>>> As for contributing I have a few small patches ready that I will send
>>>> to the list shortly. These address some of small issues regarding VHDL
>>>> code generation that I identified on another email.
>>>>
>>>> Cheers,
>>>>
>>>> Angel
>>>>
>>>
>>> Angel,
>>>
>>> Make sure you review the "Guide for Developers":
>>> http://www.myhdl.org/doku.php/dev:patches
>>>
>>> Jan D. has put together a comprehensive guide for contributing
>>> to the project.
>>>
>>> Also note,  Jan D. has the final say on all bundles submitted.
>>>
>>> Thanks for interest in contributing!
>>>
>>> Regards,
>>> Chris
>>
>> OK, I did not know about that document. Sorry.
>>
>> Apparently it seems Jan prefers to receive bundles directly on his
>> email address. I sent a patch series to the list because that is the
>> way things are done on the tortoisehg and on the mercurial mailing
>> list itself. The document seems to suggest that it is ok to send
>> patches to the list for discussion though, so I guess what I did is
>> kind of ok.
>>
>> Cheers,
>>
>> Angel
>>
>
> I usually send patches/bundles directly to the mailing-list
> (good or bad).  The issue can be if it is large for some
> reason.  I don't believe it is bad to send patches to the
> mailing-list.
>
> .chris

OK, I will not need to resend them then :-)

I tried to run the tests on my windows PC. The core tests run fine but
I have trouble running the VHDL conversion tests (which are the most
interesting ones for my patches).

I was able to run the VHDL conversion tests, but I got 5 passes and 40
failures _without_ my patches. With my patches I get the same result.
This is the output of running py.test on the
myhdl\test\conversion\toVHDL folder:

$ /c/Python27/Scripts/py.test
============================= test session starts ==============================
platform win32 -- Python 2.7.2 -- pytest-2.2.4
collecting ... collected 45 items

test_custom.py FFFF..
test_enum.py F
test_loops.py .
test_newcustom.py FFFF..
test_ops.py FFFFFFFFFFFFFF
test_signed.py FFFFFFFFFFFFFFFFF

=================================== FAILURES ===================================
__________________________________ testIncRef __________________________________

    def testIncRef():
>       assert conversion.verify(customBench, incRef) == 0
E       assert 1 == 0
E        +  where 1 = <myhdl.conversion._verify._VerificationClass
object at 0x02451830>(customBench, incRef)
E        +    where <myhdl.conversion._verify._VerificationClass
object at 0x02451830> = conversion.verify

test_custom.py:248: AssertionError
------------------------------- Captured stderr --------------------------------
customBench.vhd:59:14:warning: universal integer bound must be numeric
literal or attribute
customBench.vhd:63:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration custombench_ghdl
Conversion verification failed
___________________________________ testInc ____________________________________

    def testInc():
>       assert conversion.verify(customBench, inc) == 0
E       assert 1 == 0
E        +  where 1 = <myhdl.conversion._verify._VerificationClass
object at 0x02451830>(customBench, inc)
E        +    where <myhdl.conversion._verify._VerificationClass
object at 0x02451830> = conversion.verify

test_custom.py:251: AssertionError
------------------------------- Captured stderr --------------------------------
customBench.vhd:59:14:warning: universal integer bound must be numeric
literal or attribute
customBench.vhd:63:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration custombench_ghdl
Conversion verification failed
___________________________________ testInc2 ___________________________________

    def testInc2():
>       assert conversion.verify(customBench, inc2) == 0
E       assert 1 == 0
E        +  where 1 = <myhdl.conversion._verify._VerificationClass
object at 0x02451830>(customBench, inc2)
E        +    where <myhdl.conversion._verify._VerificationClass
object at 0x02451830> = conversion.verify

test_custom.py:254: AssertionError
------------------------------- Captured stderr --------------------------------
** ToVHDLWarning: Signal is driven but not read: inc_inst_nextCount
customBench.vhd:64:14:warning: universal integer bound must be numeric
literal or attribute
customBench.vhd:68:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration custombench_ghdl
Conversion verification failed
___________________________________ testInc3 ___________________________________

    def testInc3():
>       assert conversion.verify(customBench, inc3) == 0
E       assert 1 == 0
E        +  where 1 = <myhdl.conversion._verify._VerificationClass
object at 0x02451830>(customBench, inc3)
E        +    where <myhdl.conversion._verify._VerificationClass
object at 0x02451830> = conversion.verify

test_custom.py:257: AssertionError
------------------------------- Captured stderr --------------------------------
** ToVHDLWarning: Signal is driven but not read: inc_inst_inc2_inst_nextCount
customBench.vhd:64:14:warning: universal integer bound must be numeric
literal or attribute
customBench.vhd:68:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration custombench_ghdl
Conversion verification failed
__________________________________ test_enum ___________________________________

    def test_enum():
>       assert conversion.verify(bench_enum) == 0
E       assert 1 == 0
E        +  where 1 = <myhdl.conversion._verify._VerificationClass
object at 0x02451830>(bench_enum)
E        +    where <myhdl.conversion._verify._VerificationClass
object at 0x02451830> = conversion.verify

test_enum.py:65: AssertionError
------------------------------- Captured stderr --------------------------------
error: cannot find entity or configuration bench_enum_ghdl
Conversion verification failed
__________________________________ testIncRef __________________________________

    def testIncRef():
>       assert conversion.verify(customBench, incRef) == 0
E       assert 1 == 0
E        +  where 1 = <myhdl.conversion._verify._VerificationClass
object at 0x02451830>(customBench, incRef)
E        +    where <myhdl.conversion._verify._VerificationClass
object at 0x02451830> = conversion.verify

test_newcustom.py:248: AssertionError
------------------------------- Captured stderr --------------------------------
customBench.vhd:59:14:warning: universal integer bound must be numeric
literal or attribute
customBench.vhd:63:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration custombench_ghdl
Conversion verification failed
___________________________________ testInc ____________________________________

    def testInc():
>       assert conversion.verify(customBench, inc) == 0
E       assert 1 == 0
E        +  where 1 = <myhdl.conversion._verify._VerificationClass
object at 0x02451830>(customBench, inc)
E        +    where <myhdl.conversion._verify._VerificationClass
object at 0x02451830> = conversion.verify

test_newcustom.py:251: AssertionError
------------------------------- Captured stderr --------------------------------
customBench.vhd:59:14:warning: universal integer bound must be numeric
literal or attribute
customBench.vhd:63:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration custombench_ghdl
Conversion verification failed
___________________________________ testInc2 ___________________________________

    def testInc2():
>       assert conversion.verify(customBench, inc2) == 0
E       assert 1 == 0
E        +  where 1 = <myhdl.conversion._verify._VerificationClass
object at 0x02451830>(customBench, inc2)
E        +    where <myhdl.conversion._verify._VerificationClass
object at 0x02451830> = conversion.verify

test_newcustom.py:254: AssertionError
------------------------------- Captured stderr --------------------------------
customBench.vhd:64:14:warning: universal integer bound must be numeric
literal or attribute
customBench.vhd:68:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration custombench_ghdl
Conversion verification failed
___________________________________ testInc3 ___________________________________

    def testInc3():
>       assert conversion.verify(customBench, inc3) == 0
E       assert 1 == 0
E        +  where 1 = <myhdl.conversion._verify._VerificationClass
object at 0x02451830>(customBench, inc3)
E        +    where <myhdl.conversion._verify._VerificationClass
object at 0x02451830> = conversion.verify

test_newcustom.py:257: AssertionError
------------------------------- Captured stderr --------------------------------
customBench.vhd:64:14:warning: universal integer bound must be numeric
literal or attribute
customBench.vhd:68:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration custombench_ghdl
Conversion verification failed
________________________________ testBinary[0] _________________________________

m = 4, n = 4

    def checkBinary(m, n):
>       assert verify(binaryBench, m, n) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, 4, 4)

test_ops.py:172: AssertionError
------------------------------- Captured stderr --------------------------------
binaryBench.vhd:92:14:warning: universal integer bound must be numeric
literal or attribute
binaryBench.vhd:131:14:warning: universal integer bound must be
numeric literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
________________________________ testBinary[1] _________________________________

m = 5, n = 3

    def checkBinary(m, n):
>       assert verify(binaryBench, m, n) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, 5, 3)

test_ops.py:172: AssertionError
------------------------------- Captured stderr --------------------------------
binaryBench.vhd:92:14:warning: universal integer bound must be numeric
literal or attribute
binaryBench.vhd:115:14:warning: universal integer bound must be
numeric literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
________________________________ testBinary[2] _________________________________

m = 2, n = 6

    def checkBinary(m, n):
>       assert verify(binaryBench, m, n) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, 2, 6)

test_ops.py:172: AssertionError
------------------------------- Captured stderr --------------------------------
binaryBench.vhd:92:14:warning: universal integer bound must be numeric
literal or attribute
binaryBench.vhd:107:14:warning: universal integer bound must be
numeric literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
________________________________ testBinary[3] _________________________________

m = 8, n = 7

    def checkBinary(m, n):
>       assert verify(binaryBench, m, n) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, 8, 7)

test_ops.py:172: AssertionError
------------------------------- Captured stderr --------------------------------
binaryBench.vhd:92:14:warning: universal integer bound must be numeric
literal or attribute
binaryBench.vhd:355:14:warning: universal integer bound must be
numeric literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
_______________________________ testMultiOps[0] ________________________________

m = 4, n = 4, p = 4

    def checkMultiOps(m, n, p):
>       assert verify(multiBench, m, n, p) == 0
E       assert 1 == 0
E        +  where 1 = verify(multiBench, 4, 4, 4)

test_ops.py:264: AssertionError
------------------------------- Captured stderr --------------------------------
multiBench.vhd:45:14:warning: universal integer bound must be numeric
literal or attribute
multiBench.vhd:99:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration multibench_ghdl
Conversion verification failed
_______________________________ testMultiOps[1] ________________________________

m = 5, n = 3, p = 2

    def checkMultiOps(m, n, p):
>       assert verify(multiBench, m, n, p) == 0
E       assert 1 == 0
E        +  where 1 = verify(multiBench, 5, 3, 2)

test_ops.py:264: AssertionError
------------------------------- Captured stderr --------------------------------
multiBench.vhd:45:14:warning: universal integer bound must be numeric
literal or attribute
multiBench.vhd:63:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration multibench_ghdl
Conversion verification failed
_______________________________ testMultiOps[2] ________________________________

m = 3, n = 4, p = 6

    def checkMultiOps(m, n, p):
>       assert verify(multiBench, m, n, p) == 0
E       assert 1 == 0
E        +  where 1 = verify(multiBench, 3, 4, 6)

test_ops.py:264: AssertionError
------------------------------- Captured stderr --------------------------------
multiBench.vhd:45:14:warning: universal integer bound must be numeric
literal or attribute
multiBench.vhd:75:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration multibench_ghdl
Conversion verification failed
_______________________________ testMultiOps[3] ________________________________

m = 3, n = 7, p = 4

    def checkMultiOps(m, n, p):
>       assert verify(multiBench, m, n, p) == 0
E       assert 1 == 0
E        +  where 1 = verify(multiBench, 3, 7, 4)

test_ops.py:264: AssertionError
------------------------------- Captured stderr --------------------------------
multiBench.vhd:45:14:warning: universal integer bound must be numeric
literal or attribute
multiBench.vhd:75:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration multibench_ghdl
Conversion verification failed
_______________________________ testUnaryOps[0] ________________________________

m = 4

    def checkUnaryOps(m):
>       assert verify(unaryBench, m) == 0
E       assert 1 == 0
E        +  where 1 = verify(unaryBench, 4)

test_ops.py:326: AssertionError
------------------------------- Captured stderr --------------------------------
unaryBench.vhd:37:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration unarybench_ghdl
Conversion verification failed
_______________________________ testUnaryOps[1] ________________________________

m = 7

    def checkUnaryOps(m):
>       assert verify(unaryBench, m) == 0
E       assert 1 == 0
E        +  where 1 = verify(unaryBench, 7)

test_ops.py:326: AssertionError
------------------------------- Captured stderr --------------------------------
unaryBench.vhd:37:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration unarybench_ghdl
Conversion verification failed
________________________________ testAugmOps[0] ________________________________

m = 4, n = 4

    def checkAugmOps(m, n):
>       assert verify(augmBench, m, n) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, 4, 4)

test_ops.py:466: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:98:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
________________________________ testAugmOps[1] ________________________________

m = 5, n = 3

    def checkAugmOps(m, n):
>       assert verify(augmBench, m, n) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, 5, 3)

test_ops.py:466: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:98:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
________________________________ testAugmOps[2] ________________________________

m = 2, n = 6

    def checkAugmOps(m, n):
>       assert verify(augmBench, m, n) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, 2, 6)

test_ops.py:466: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:98:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
________________________________ testAugmOps[3] ________________________________

m = 8, n = 7

    def checkAugmOps(m, n):
>       assert verify(augmBench, m, n) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, 8, 7)

test_ops.py:466: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:98:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
_______________________________ testBinaryOps[0] _______________________________

Ll = -254, Ml = 236, Lr = 0, Mr = 4

    def checkBinaryOps( Ll, Ml, Lr, Mr):
>       assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, -254, 236, 0, 4)

test_signed.py:188: AssertionError
------------------------------- Captured stderr --------------------------------
** ToVHDLWarning: Signal is not driven: RightShift
binaryBench.vhd:69:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
_______________________________ testBinaryOps[1] _______________________________

Ll = -128, Ml = 128, Lr = -128, Mr = 128

    def checkBinaryOps( Ll, Ml, Lr, Mr):
>       assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, -128, 128, -128, 128)

test_signed.py:188: AssertionError
------------------------------- Captured stderr --------------------------------
binaryBench.vhd:69:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
_______________________________ testBinaryOps[2] _______________________________

Ll = -53, Ml = 25, Lr = -23, Mr = 123

    def checkBinaryOps( Ll, Ml, Lr, Mr):
>       assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, -53, 25, -23, 123)

test_signed.py:188: AssertionError
------------------------------- Captured stderr --------------------------------
binaryBench.vhd:69:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
_______________________________ testBinaryOps[3] _______________________________

Ll = -23, Ml = 145, Lr = -66, Mr = 12

    def checkBinaryOps( Ll, Ml, Lr, Mr):
>       assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, -23, 145, -66, 12)

test_signed.py:188: AssertionError
------------------------------- Captured stderr --------------------------------
binaryBench.vhd:69:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
_______________________________ testBinaryOps[4] _______________________________

Ll = 23, Ml = 34, Lr = -34, Mr = -16

    def checkBinaryOps( Ll, Ml, Lr, Mr):
>       assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, 23, 34, -34, -16)

test_signed.py:188: AssertionError
------------------------------- Captured stderr --------------------------------
binaryBench.vhd:69:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
_______________________________ testBinaryOps[5] _______________________________

Ll = -54, Ml = -20, Lr = 45, Mr = 73

    def checkBinaryOps( Ll, Ml, Lr, Mr):
>       assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, -54, -20, 45, 73)

test_signed.py:188: AssertionError
------------------------------- Captured stderr --------------------------------
binaryBench.vhd:69:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
_______________________________ testBinaryOps[6] _______________________________

Ll = -25, Ml = -12, Lr = -123, Mr = -66

    def checkBinaryOps( Ll, Ml, Lr, Mr):
>       assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0
E       assert 1 == 0
E        +  where 1 = verify(binaryBench, -25, -12, -123, -66)

test_signed.py:188: AssertionError
------------------------------- Captured stderr --------------------------------
binaryBench.vhd:69:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration binarybench_ghdl
Conversion verification failed
_______________________________ testUnaryOps[0] ________________________________

m = 4

    def checkUnaryOps(m):
>       assert verify(unaryBench, m) == 0
E       assert 1 == 0
E        +  where 1 = verify(unaryBench, 4)

test_signed.py:266: AssertionError
------------------------------- Captured stderr --------------------------------
unaryBench.vhd:37:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration unarybench_ghdl
Conversion verification failed
_______________________________ testUnaryOps[1] ________________________________

m = 7

    def checkUnaryOps(m):
>       assert verify(unaryBench, m) == 0
E       assert 1 == 0
E        +  where 1 = verify(unaryBench, 7)

test_signed.py:266: AssertionError
------------------------------- Captured stderr --------------------------------
unaryBench.vhd:37:14:warning: universal integer bound must be numeric
literal or attribute
error: cannot find entity or configuration unarybench_ghdl
Conversion verification failed
________________________________ testAugmOps[0] ________________________________

Ll = -254, Ml = 236, Lr = 0, Mr = 4

    def checkAugmOps( Ll, Ml, Lr, Mr):
>       assert verify(augmBench, Ll, Ml, Lr, Mr) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, -254, 236, 0, 4)

test_signed.py:412: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:60:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
________________________________ testAugmOps[1] ________________________________

Ll = -128, Ml = 128, Lr = -128, Mr = 128

    def checkAugmOps( Ll, Ml, Lr, Mr):
>       assert verify(augmBench, Ll, Ml, Lr, Mr) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, -128, 128, -128, 128)

test_signed.py:412: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:60:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
________________________________ testAugmOps[2] ________________________________

Ll = -53, Ml = 25, Lr = -23, Mr = 123

    def checkAugmOps( Ll, Ml, Lr, Mr):
>       assert verify(augmBench, Ll, Ml, Lr, Mr) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, -53, 25, -23, 123)

test_signed.py:412: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:60:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
________________________________ testAugmOps[3] ________________________________

Ll = -23, Ml = 145, Lr = -66, Mr = 12

    def checkAugmOps( Ll, Ml, Lr, Mr):
>       assert verify(augmBench, Ll, Ml, Lr, Mr) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, -23, 145, -66, 12)

test_signed.py:412: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:60:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
________________________________ testAugmOps[4] ________________________________

Ll = 23, Ml = 34, Lr = -34, Mr = -16

    def checkAugmOps( Ll, Ml, Lr, Mr):
>       assert verify(augmBench, Ll, Ml, Lr, Mr) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, 23, 34, -34, -16)

test_signed.py:412: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:60:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
________________________________ testAugmOps[5] ________________________________

Ll = -54, Ml = -20, Lr = 45, Mr = 73

    def checkAugmOps( Ll, Ml, Lr, Mr):
>       assert verify(augmBench, Ll, Ml, Lr, Mr) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, -54, -20, 45, 73)

test_signed.py:412: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:60:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
________________________________ testAugmOps[6] ________________________________

Ll = -25, Ml = -12, Lr = -123, Mr = -66

    def checkAugmOps( Ll, Ml, Lr, Mr):
>       assert verify(augmBench, Ll, Ml, Lr, Mr) == 0
E       assert 1 == 0
E        +  where 1 = verify(augmBench, -25, -12, -123, -66)

test_signed.py:412: AssertionError
------------------------------- Captured stderr --------------------------------
augmBench.vhd:60:14:warning: universal integer bound must be numeric
literal or attribute
<class 'myhdl.StopSimulation'>: No more events
error: cannot find entity or configuration augmbench_ghdl
Conversion verification failed
_______________________________ testExpressions ________________________________

    def testExpressions():
>       assert verify(expressionsBench) == 0
E       assert 1 == 0
E        +  where 1 = verify(expressionsBench)

test_signed.py:503: AssertionError
------------------------------- Captured stderr --------------------------------
error: cannot find entity or configuration expressionsbench_ghdl
Conversion verification failed
===================== 40 failed, 5 passed in 16.95 seconds =====================


Cheers,

Angel

Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Christopher F. <chr...@gm...>]

On 10/10/2012 11:04 AM, Angel Ezquerra wrote:
> On Wed, Oct 10, 2012 at 5:56 PM, Christopher Felton
> <chr...@gm...> wrote:
>> On 10/10/2012 10:46 AM, Angel Ezquerra wrote:
>>> On Wed, Oct 10, 2012 at 2:25 PM, Christopher Felton
>>> <chr...@gm...> wrote:
>>>> <snip>
>>>>>
>>>>>
>>>>>>> Anyway, since this process seems easy to automate (I can't really
>>>>>>> tell, since I don't really understand it), the obvious question is why
>>>>>>> not make MyHDL itself automate it for us? That should put to rest the
>>>>>>> question of generating hierarchical VHDL or Verilog code which seems
>>>>>>> to crop up regularly on this list and on other online discussions
>>>>>>> about MyHDL!
>>>>>>
>>>>>> The obvious question is why someone interested in a
>>>>>> feature doesn't propose a MEP and a patch?
>>>>>
>>>>> That is a fair point. I am still "testing the waters" with MyHDL so to
>>>>> speak, so for now I am just raising the concerns that I come up with.
>>>>>
>>>>> I could try to write a MEP but first I'd like to see if there is some
>>>>> consensus that this could be a worthy idea (as I believe it is). Also,
>>>>> what would be the preferred way to indicate that a group of generators
>>>>> should be grouped into an entity and placed on their own file?
>>>>>
>>>>> For example, in the case that you described, imagine that you had had
>>>>> a magic wand that let you modify MyHDL in a way that you could have
>>>>> avoided all the manual work involved in solving your problem. How
>>>>> would you have liked to be able to tell MyHDL that you wanted to place
>>>>> "submodule" on its own file?
>>>>>
>>>>> Contributing a patch is another matter though. I am quite busy
>>>>> contributing to TortoiseHg at the moment and I don't know how complex
>>>>> the MyHDL code base is. I don't know that I'd have the time to dig
>>>>> deep enough into it to contribute such a patch.
>>>>>
>>>>
>>>> I am having a hard time following you.  At one point
>>>> you comment
>>>>
>>>>       "since this process seems easy to automate ..."
>>>>
>>>> then you comment
>>>>
>>>>       "... the amount of steps would be great"
>>>>       (implying difficulty)
>>>>
>>>> But if it is easy to automate why would we be concerned
>>>> with the number of steps?
>>>
>>> I should have been more clear:
>>> - The process "seems easy to automate" according to what you said.
>>> - But it _currently_ requires a great number of steps since it must be
>>> performed _manually_ (which does not necessarily mean that it would be
>>> hard, just tiresome).
>>>
>>> That is, currently MyHDL does not provide a way to make this without
>>> too much effort, but apparently (from what you said) it should be
>>> possible to make it automatic.
>>>
>>>> I also get confused if you are only interested in an
>>>> existing solution or you are willing to experiment and
>>>> be part of a development.  This conversation seems to
>>>> bounce back and forth between wanting a working solution
>>>> and "testing the waters".  I am never sure which I am
>>>> replying to.  Given the comments above, I assume you
>>>> are mainly interested in existing and working solutions.
>>>>
>>>> Maintaining hierarchy during conversion is a reasonable
>>>> feature request.  But the priority of the feature?  And
>>>> the best path forward?  I think it is safe to say, given
>>>> the resources available this feature will not be added
>>>> any time soon.  I think you are simply trying to stimulate
>>>> conversation and ideas (which is good!).  But I don't believe
>>>> anyone has the bandwidth to experiment and implement the
>>>> feature.
>>>
>>> I'm mostly interested on working solutions, but since it seems there
>>> are none (at least not experimental ones), I want to spur the
>>> conversation some and show that there are people (at least one! :-)
>>> interested on this feature.
>>>
>>> As for contributing I have a few small patches ready that I will send
>>> to the list shortly. These address some of small issues regarding VHDL
>>> code generation that I identified on another email.
>>>
>>> Cheers,
>>>
>>> Angel
>>>
>>
>> Angel,
>>
>> Make sure you review the "Guide for Developers":
>> http://www.myhdl.org/doku.php/dev:patches
>>
>> Jan D. has put together a comprehensive guide for contributing
>> to the project.
>>
>> Also note,  Jan D. has the final say on all bundles submitted.
>>
>> Thanks for interest in contributing!
>>
>> Regards,
>> Chris
>
> OK, I did not know about that document. Sorry.
>
> Apparently it seems Jan prefers to receive bundles directly on his
> email address. I sent a patch series to the list because that is the
> way things are done on the tortoisehg and on the mercurial mailing
> list itself. The document seems to suggest that it is ok to send
> patches to the list for discussion though, so I guess what I did is
> kind of ok.
>
> Cheers,
>
> Angel
>

I usually send patches/bundles directly to the mailing-list
(good or bad).  The issue can be if it is large for some
reason.  I don't believe it is bad to send patches to the
mailing-list.

.chris

Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Angel E. <ang...@gm...>]

On Wed, Oct 10, 2012 at 5:56 PM, Christopher Felton
<chr...@gm...> wrote:
> On 10/10/2012 10:46 AM, Angel Ezquerra wrote:
>> On Wed, Oct 10, 2012 at 2:25 PM, Christopher Felton
>> <chr...@gm...> wrote:
>>> <snip>
>>>>
>>>>
>>>>>> Anyway, since this process seems easy to automate (I can't really
>>>>>> tell, since I don't really understand it), the obvious question is why
>>>>>> not make MyHDL itself automate it for us? That should put to rest the
>>>>>> question of generating hierarchical VHDL or Verilog code which seems
>>>>>> to crop up regularly on this list and on other online discussions
>>>>>> about MyHDL!
>>>>>
>>>>> The obvious question is why someone interested in a
>>>>> feature doesn't propose a MEP and a patch?
>>>>
>>>> That is a fair point. I am still "testing the waters" with MyHDL so to
>>>> speak, so for now I am just raising the concerns that I come up with.
>>>>
>>>> I could try to write a MEP but first I'd like to see if there is some
>>>> consensus that this could be a worthy idea (as I believe it is). Also,
>>>> what would be the preferred way to indicate that a group of generators
>>>> should be grouped into an entity and placed on their own file?
>>>>
>>>> For example, in the case that you described, imagine that you had had
>>>> a magic wand that let you modify MyHDL in a way that you could have
>>>> avoided all the manual work involved in solving your problem. How
>>>> would you have liked to be able to tell MyHDL that you wanted to place
>>>> "submodule" on its own file?
>>>>
>>>> Contributing a patch is another matter though. I am quite busy
>>>> contributing to TortoiseHg at the moment and I don't know how complex
>>>> the MyHDL code base is. I don't know that I'd have the time to dig
>>>> deep enough into it to contribute such a patch.
>>>>
>>>
>>> I am having a hard time following you.  At one point
>>> you comment
>>>
>>>      "since this process seems easy to automate ..."
>>>
>>> then you comment
>>>
>>>      "... the amount of steps would be great"
>>>      (implying difficulty)
>>>
>>> But if it is easy to automate why would we be concerned
>>> with the number of steps?
>>
>> I should have been more clear:
>> - The process "seems easy to automate" according to what you said.
>> - But it _currently_ requires a great number of steps since it must be
>> performed _manually_ (which does not necessarily mean that it would be
>> hard, just tiresome).
>>
>> That is, currently MyHDL does not provide a way to make this without
>> too much effort, but apparently (from what you said) it should be
>> possible to make it automatic.
>>
>>> I also get confused if you are only interested in an
>>> existing solution or you are willing to experiment and
>>> be part of a development.  This conversation seems to
>>> bounce back and forth between wanting a working solution
>>> and "testing the waters".  I am never sure which I am
>>> replying to.  Given the comments above, I assume you
>>> are mainly interested in existing and working solutions.
>>>
>>> Maintaining hierarchy during conversion is a reasonable
>>> feature request.  But the priority of the feature?  And
>>> the best path forward?  I think it is safe to say, given
>>> the resources available this feature will not be added
>>> any time soon.  I think you are simply trying to stimulate
>>> conversation and ideas (which is good!).  But I don't believe
>>> anyone has the bandwidth to experiment and implement the
>>> feature.
>>
>> I'm mostly interested on working solutions, but since it seems there
>> are none (at least not experimental ones), I want to spur the
>> conversation some and show that there are people (at least one! :-)
>> interested on this feature.
>>
>> As for contributing I have a few small patches ready that I will send
>> to the list shortly. These address some of small issues regarding VHDL
>> code generation that I identified on another email.
>>
>> Cheers,
>>
>> Angel
>>
>
> Angel,
>
> Make sure you review the "Guide for Developers":
> http://www.myhdl.org/doku.php/dev:patches
>
> Jan D. has put together a comprehensive guide for contributing
> to the project.
>
> Also note,  Jan D. has the final say on all bundles submitted.
>
> Thanks for interest in contributing!
>
> Regards,
> Chris

OK, I did not know about that document. Sorry.

Apparently it seems Jan prefers to receive bundles directly on his
email address. I sent a patch series to the list because that is the
way things are done on the tortoisehg and on the mercurial mailing
list itself. The document seems to suggest that it is ok to send
patches to the list for discussion though, so I guess what I did is
kind of ok.

Cheers,

Angel

Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Christopher F. <chr...@gm...>]

On 10/10/2012 10:46 AM, Angel Ezquerra wrote:
> On Wed, Oct 10, 2012 at 2:25 PM, Christopher Felton
> <chr...@gm...> wrote:
>> <snip>
>>>
>>>
>>>>> Anyway, since this process seems easy to automate (I can't really
>>>>> tell, since I don't really understand it), the obvious question is why
>>>>> not make MyHDL itself automate it for us? That should put to rest the
>>>>> question of generating hierarchical VHDL or Verilog code which seems
>>>>> to crop up regularly on this list and on other online discussions
>>>>> about MyHDL!
>>>>
>>>> The obvious question is why someone interested in a
>>>> feature doesn't propose a MEP and a patch?
>>>
>>> That is a fair point. I am still "testing the waters" with MyHDL so to
>>> speak, so for now I am just raising the concerns that I come up with.
>>>
>>> I could try to write a MEP but first I'd like to see if there is some
>>> consensus that this could be a worthy idea (as I believe it is). Also,
>>> what would be the preferred way to indicate that a group of generators
>>> should be grouped into an entity and placed on their own file?
>>>
>>> For example, in the case that you described, imagine that you had had
>>> a magic wand that let you modify MyHDL in a way that you could have
>>> avoided all the manual work involved in solving your problem. How
>>> would you have liked to be able to tell MyHDL that you wanted to place
>>> "submodule" on its own file?
>>>
>>> Contributing a patch is another matter though. I am quite busy
>>> contributing to TortoiseHg at the moment and I don't know how complex
>>> the MyHDL code base is. I don't know that I'd have the time to dig
>>> deep enough into it to contribute such a patch.
>>>
>>
>> I am having a hard time following you.  At one point
>> you comment
>>
>>      "since this process seems easy to automate ..."
>>
>> then you comment
>>
>>      "... the amount of steps would be great"
>>      (implying difficulty)
>>
>> But if it is easy to automate why would we be concerned
>> with the number of steps?
>
> I should have been more clear:
> - The process "seems easy to automate" according to what you said.
> - But it _currently_ requires a great number of steps since it must be
> performed _manually_ (which does not necessarily mean that it would be
> hard, just tiresome).
>
> That is, currently MyHDL does not provide a way to make this without
> too much effort, but apparently (from what you said) it should be
> possible to make it automatic.
>
>> I also get confused if you are only interested in an
>> existing solution or you are willing to experiment and
>> be part of a development.  This conversation seems to
>> bounce back and forth between wanting a working solution
>> and "testing the waters".  I am never sure which I am
>> replying to.  Given the comments above, I assume you
>> are mainly interested in existing and working solutions.
>>
>> Maintaining hierarchy during conversion is a reasonable
>> feature request.  But the priority of the feature?  And
>> the best path forward?  I think it is safe to say, given
>> the resources available this feature will not be added
>> any time soon.  I think you are simply trying to stimulate
>> conversation and ideas (which is good!).  But I don't believe
>> anyone has the bandwidth to experiment and implement the
>> feature.
>
> I'm mostly interested on working solutions, but since it seems there
> are none (at least not experimental ones), I want to spur the
> conversation some and show that there are people (at least one! :-)
> interested on this feature.
>
> As for contributing I have a few small patches ready that I will send
> to the list shortly. These address some of small issues regarding VHDL
> code generation that I identified on another email.
>
> Cheers,
>
> Angel
>

Angel,

Make sure you review the "Guide for Developers":
http://www.myhdl.org/doku.php/dev:patches

Jan D. has put together a comprehensive guide for contributing
to the project.

Also note,  Jan D. has the final say on all bundles submitted.

Thanks for interest in contributing!

Regards,
Chris

Re: [myhdl-list] [PATCH RFC] toVHDL: add signal attribute support

[Angel E. <ang...@gm...>]

This patch is unrelated to the ones I sent before and it will probably
be more controversial. That is why I marked it as RFC, i.e. Request
For Comments, as is often done in other mailing lists.

It adds a way to add signal attributes to the VHDL code. I tried to
follow the style of the rest of the code but I am sure there are
things that I could have done differently.

Comments are welcome.

Cheers,

Angel


On Wed, Oct 10, 2012 at 5:49 PM, Angel Ezquerra
<ang...@gm...> wrote:
> # HG changeset patch
> # User Angel Ezquerra <ang...@gm...>
> # Date 1349884148 -7200
> # Branch 0.8-dev
> # Node ID cdd0b98bc565ce08c5ab47417551e7719313d9ce
> # Parent  58ac2e97c7efbe7e3c9784b8ac25218daa056e40
> toVHDL: add signal attribute support
>
> This adds a new setAttribute() method to the Signal type, which lets the user
> set attributes that will be set on the VHDL output.
>
> In order to make it easy to avoid declaring the same attribute more than once,
> all the signal attributes are written toguether, after all signal declarations.
>
> The setAttribute() Signal method has the following interface:
>
>     Signal.setAttribute(attribute_name, attribute_value, [attribute_type])
>
> If attribute_type is not set it will default to string.
>
> diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py
> --- a/myhdl/_Signal.py
> +++ b/myhdl/_Signal.py
> @@ -107,10 +107,10 @@
>                   '_code', '_tracing', '_nrbits', '_checkVal',
>                   '_setNextVal', '_copyVal2Next', '_printVcd',
>                   '_driven' ,'_read', '_name', '_used', '_inList',
> -                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs'
> +                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs',
> +                 'setAttribute', '_attributes'
>                  )
>
> -
>      def __init__(self, val=None):
>          """ Construct a signal.
>
> @@ -118,6 +118,7 @@
>
>          """
>          self._init = deepcopy(val)
> +        self._attributes = {}
>          self._val = deepcopy(val)
>          self._next = deepcopy(val)
>          self._min = self._max = None
> @@ -300,6 +301,9 @@
>      def _printVcdVec(self):
>          print >> sim._tf, "b%s %s" % (bin(self._val, self._nrbits), self._code)
>
> +    def setAttribute(self, name, value, attribute_type=None):
> +        self._attributes[name] = (value, attribute_type)
> +
>      ### use call interface for shadow signals ###
>      def __call__(self, left, right=None):
>          s = _SliceSignal(self, left, right)
> diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
> --- a/myhdl/conversion/_toVHDL.py
> +++ b/myhdl/conversion/_toVHDL.py
> @@ -286,6 +286,22 @@
>
>  constwires = []
>
> +def _writeAttributes(f, siglist):
> +    declared_attributes = set()
> +    for s in siglist:
> +        for name in s._attributes:
> +            value, attribute_type = s._attributes[name]
> +            if attribute_type is None:
> +                # consider all attributes strings by default
> +                attribute_type = 'string'
> +                if isinstance(value, int):
> +                    attribute_type = 'integer'
> +            if name not in declared_attributes:
> +                declared_attributes.add(name)
> +                print >> f, "    attribute %s : %s;" % (name, attribute_type)
> +
> +                value = '"%s"' % value
> +            print >> f, "    attribute %s of %s: signal is %s" % (name, s._name, value)
>
>  def _writeSigDecls(f, intf, siglist, memlist):
>      del constwires[:]
> @@ -329,6 +345,9 @@
>          t = "t_array_%s" % m.name
>          print >> f, "    type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r)
>          print >> f, "    signal %s: %s;" % (m.name, t)
> +
> +    _writeAttributes(f, siglist + memlist)
> +
>      print >> f
>
>  def _writeCompDecls(f,  compDecls):
>
> ------------------------------------------------------------------------------
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>

[myhdl-list] [PATCH RFC] toVHDL: add signal attribute support

[Angel E. <ang...@gm...>]

# HG changeset patch
# User Angel Ezquerra <ang...@gm...>
# Date 1349884148 -7200
# Branch 0.8-dev
# Node ID cdd0b98bc565ce08c5ab47417551e7719313d9ce
# Parent  58ac2e97c7efbe7e3c9784b8ac25218daa056e40
toVHDL: add signal attribute support

This adds a new setAttribute() method to the Signal type, which lets the user
set attributes that will be set on the VHDL output.

In order to make it easy to avoid declaring the same attribute more than once,
all the signal attributes are written toguether, after all signal declarations.

The setAttribute() Signal method has the following interface:

    Signal.setAttribute(attribute_name, attribute_value, [attribute_type])

If attribute_type is not set it will default to string.

diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py
--- a/myhdl/_Signal.py
+++ b/myhdl/_Signal.py
@@ -107,10 +107,10 @@
                  '_code', '_tracing', '_nrbits', '_checkVal', 
                  '_setNextVal', '_copyVal2Next', '_printVcd', 
                  '_driven' ,'_read', '_name', '_used', '_inList',
-                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs'
+                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs',
+                 'setAttribute', '_attributes'
                 )
 
-
     def __init__(self, val=None):
         """ Construct a signal.
 
@@ -118,6 +118,7 @@
         
         """
         self._init = deepcopy(val)
+        self._attributes = {}
         self._val = deepcopy(val)
         self._next = deepcopy(val)
         self._min = self._max = None
@@ -300,6 +301,9 @@
     def _printVcdVec(self):
         print >> sim._tf, "b%s %s" % (bin(self._val, self._nrbits), self._code)
 
+    def setAttribute(self, name, value, attribute_type=None):
+        self._attributes[name] = (value, attribute_type)
+
     ### use call interface for shadow signals ###
     def __call__(self, left, right=None):
         s = _SliceSignal(self, left, right)
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -286,6 +286,22 @@
 
 constwires = []
 
+def _writeAttributes(f, siglist):
+    declared_attributes = set()
+    for s in siglist:
+        for name in s._attributes:
+            value, attribute_type = s._attributes[name]
+            if attribute_type is None:
+                # consider all attributes strings by default
+                attribute_type = 'string'
+                if isinstance(value, int):
+                    attribute_type = 'integer'
+            if name not in declared_attributes:
+                declared_attributes.add(name)
+                print >> f, "    attribute %s : %s;" % (name, attribute_type)
+            
+                value = '"%s"' % value
+            print >> f, "    attribute %s of %s: signal is %s" % (name, s._name, value)
 
 def _writeSigDecls(f, intf, siglist, memlist):
     del constwires[:]
@@ -329,6 +345,9 @@
         t = "t_array_%s" % m.name
         print >> f, "    type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r)
         print >> f, "    signal %s: %s;" % (m.name, t)
+
+    _writeAttributes(f, siglist + memlist)
+
     print >> f
 
 def _writeCompDecls(f,  compDecls):

[myhdl-list] [PATCH 3 of 3] toVHDL: place entity documentation above the entity declaration

[Angel E. <ang...@gm...>]

# HG changeset patch
# User Angel Ezquerra <ang...@gm...>
# Date 1349882593 -7200
# Branch 0.8-dev
# Node ID 58ac2e97c7efbe7e3c9784b8ac25218daa056e40
# Parent  54652ce766a4f8ee6318e662a5394df20a899711
toVHDL: place entity documentation above the entity declaration

Up until now the entity documentation was placed betweent he entity and the
architecture, which is an unusual location for entity level documentation.

diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -241,6 +241,7 @@
     if needPck:
         print >> f, "use %s.pck_%s.all;" % (lib, intf.name)
         print >> f
+    print >> f, doc
     print >> f, "entity %s is" % intf.name
     if intf.argnames:
         f.write("    port (")
@@ -273,7 +274,6 @@
                 f.write("\n        %s: in %s%s" % (portname, p, r))
         f.write("\n    );\n")
     print >> f, "end entity %s;" % intf.name
-    print >> f, doc
     print >> f
     print >> f, "architecture %s of %s is" % (arch, intf.name)
     print >> f