myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Newbie questions

[Christopher F. <chr...@gm...>]

On Wed, Sep 14, 2016 at 4:39 PM, Mark Haun <ma...@ha...> wrote:

> Hi everyone,
>
> This is my first post to the list.  I'm new to MyHDL, using it with a
> Digilent "Arty" board and Vivado to learn FPGAs and HDL in general.  So
> far,
> I've found the documentation to be excellent and I haven't had any problems
> with simple LED flashing, PWM, etc.  Along the way I've accumulated some
> questions however:
>

Welcome,

A quick note, for the most part we have moved
conversations to discourse.myhdl.org, you might
get more responses there.


>
> 1) I would like to parameterize certain hardware modules like I see in the
> examples, e.g. I have the following "Timepulse" module:
>
> def Timepulse(reset, clk, q, interval=int(100e6)):
>     """ Generate a pulse for one clock cycle every <interval> clock cycles
>
>     q       timepulse output, with period equal to one clock
>     """
>     count = Signal(intbv(0, min=0, max=interval))
>
> Here "interval" is intended to be taken as a constant, for the purposes of
> simulation and conversion.  However, the Python code
>
>         if count == interval - 1:
>             count.next = 0
>         else:
>             count.next = count + 1
>
>         if count == interval - 1:
>             q.next = 1
>         elif count == 0:
>             q.next = 0
>
> is converted to the following Verilog:
>
>         if (($signed({1'b0, count}) == (100000000 - 1))) begin
>             count <= 0;
>         end
>         else begin
>             count <= (count + 1);
>         end
>         case (count)
>             (-'h1): begin
>                 q <= 1;
>             end
>             'h0: begin
>                 q <= 0;
>             end
>         endcase
>
> I don't understand where all the signed-arithmetic handling comes from.
> Intuitively, I thought the Verilog should be the same whether my expression
> uses "interval-1" or "interval", because both are large positive constants
> within the range of the count intbv.  But in fact when I take away the -1,
> the signed-number handling goes away too.  What am I missing?
>
> Something looks odd, someone will need to,
investigate a work around in the near term
is to use a separate variable

    countmax = interval-1
    # ...
    @always
        ...
        if count == countmax



> 2) When converting to Verilog, do the input/output port names always follow
> the names in the definition of the top-level Python function?  E.g. in the
> StopWatch tutorial, we have
>
> def StopWatch(tens_led, ones_led, tenths_led, startstop, reset, clock):
>
> so upon conversion, the Verilog code uses the names "tens_led", "ones_led",
> etc. as the inputs and outputs.  But when targeting a dev board, I would
> like to assign those ports to existing port names defined in my constraints
> file.
>
> It seems like there should be a way to give these names when I instantiate
> StopWatch, instead of having to make the names match between my Python code
> (at a high and logical level) and my constraints file (at a low and
> hardware
> level).  Am I missing some alternative?
>

The converted top-level block names will be the
port names in the converted verilog module.

Regards,
Chris


>
>

[myhdl-list] Newbie questions

[Mark H. <ma...@ha...>]

Hi everyone,

This is my first post to the list.  I'm new to MyHDL, using it with a
Digilent "Arty" board and Vivado to learn FPGAs and HDL in general.  So far,
I've found the documentation to be excellent and I haven't had any problems
with simple LED flashing, PWM, etc.  Along the way I've accumulated some
questions however:

1) I would like to parameterize certain hardware modules like I see in the
examples, e.g. I have the following "Timepulse" module:

def Timepulse(reset, clk, q, interval=int(100e6)):
    """ Generate a pulse for one clock cycle every <interval> clock cycles
    
    q       timepulse output, with period equal to one clock
    """
    count = Signal(intbv(0, min=0, max=interval))

Here "interval" is intended to be taken as a constant, for the purposes of
simulation and conversion.  However, the Python code

        if count == interval - 1:
            count.next = 0
        else:
            count.next = count + 1

        if count == interval - 1:
            q.next = 1
        elif count == 0:
            q.next = 0

is converted to the following Verilog:

        if (($signed({1'b0, count}) == (100000000 - 1))) begin
            count <= 0;
        end
        else begin
            count <= (count + 1);
        end
        case (count)
            (-'h1): begin
                q <= 1;
            end
            'h0: begin
                q <= 0;
            end
        endcase

I don't understand where all the signed-arithmetic handling comes from. 
Intuitively, I thought the Verilog should be the same whether my expression
uses "interval-1" or "interval", because both are large positive constants
within the range of the count intbv.  But in fact when I take away the -1,
the signed-number handling goes away too.  What am I missing?


2) When converting to Verilog, do the input/output port names always follow
the names in the definition of the top-level Python function?  E.g. in the
StopWatch tutorial, we have

def StopWatch(tens_led, ones_led, tenths_led, startstop, reset, clock):

so upon conversion, the Verilog code uses the names "tens_led", "ones_led",
etc. as the inputs and outputs.  But when targeting a dev board, I would
like to assign those ports to existing port names defined in my constraints
file.

It seems like there should be a way to give these names when I instantiate
StopWatch, instead of having to make the names match between my Python code
(at a high and logical level) and my constraints file (at a low and hardware
level).  Am I missing some alternative?


Thanks,

Mark

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Re: [myhdl-list] ExtractHierarchyError

[Md B. M. <mma...@vo...>]

Wesley New <wesley <at> ska.ac.za> writes:

> 
> 
> Yes, Chris and Jan are right.
> 
> If you have the wrong amount of objects being returned you get an 
error saying as as much. 
> 
> I was returning the correct amount of objects, but one was a Signal 
and not a Method.
> 
> 
> Thanks
> 
> Wes
> 
> On Tue, Jul 3, 2012 at 1:30 PM, Jan Decaluwe <jan <at> 
jandecaluwe.com> wrote:
> On 06/30/2012 10:50 PM, Wesley New wrote:
> > I am getting this error when running the toVerilog method:
> >
> > raise ExtractHierarchyError(_error.InconsistentToplevel % 
(top_inst.level, name))
> > myhdl.ExtractHierarchyError: Inconsistent top level 2 for toplevel - 
should be 1
> >
> > Can anyone shed some more light on this error.
> Something strange with the hierarchy definition, as
> Chris F points out you should check whether all
> modules return generators/instances correctly.
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
> 
> ----------------------------------------------------------------------
--------
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> _______________________________________________
> myhdl-list mailing listmyhdl-list <at> 
lists.sourceforge.nethttps://lists.sourceforge.net/lists/listinfo/myhdl-
list
> 
> 
> 
> 
> 
> 
> 
> 
> ----------------------------------------------------------------------
--------
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Discussions 
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malware 
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> 
> _______________________________________________
> myhdl-list mailing list
> myhdl-list <at> lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
> 
Yes, this is due to incorrect return of a function. Sometimes we forget 
to include the return statement at the end of a module, or make spelling 
mistake in the return value. Thats are some possible reasons behind the 
error

Re: [myhdl-list] some issue

[Christopher F. <chr...@gm...>]

Chriss,

Thanks for the input, couple things.  Most discussions have
been moved to discourse.myhdl.org (forum) and gitter.  You
might get more responses on discourse.

Error reporting can always use improvement but finding the
resources and a useful method is a little trickier.

One of our GSoC students also ran into "C" and it is difficult
to debug.  Maybe we can encourage him to add some additional
reporting.

Regards,
Chris

On Wed, Jun 22, 2016 at 11:45 AM, <chr...@si...> wrote:

> Dear all,
>
> When I using myhdl, I found some issue that could be improvement as
> following for discussion
>
> A)  information for debug is not enough
>       For example, I build some basic library.  when something wrong (e.g
> multiple driven ),  myhdl only report the location happens in the library
> in conversion, but not tell me where I call the library.
>
> I try to modify the the Error class to add a "node" property, then use
> "try .. exception" to catch the node information as following.
> class Error(Exception):
>
>     def __init__(self, kind, msg="", info="",node=None):
>         self.kind = kind
>         self.msg = msg
>         self.info = info
>         self.node = node
>
>    The solution is helpful, but not convenient.  It's better to
> automatically locate the root cause of the error.
>
>
> B)  In simulation, there is similar issue when use lot of library as issue
> A.  But I have no ideas to add debug info (need more time to figure out the
> simulation mechanism, currently not document found)
>
> C) in python 3.5,  the following will report a "n.signed" error ( n has no
> attribute of "signed")
>     @myhdl.always_comb
>      def rtl():
>          if   a == True:
>               do_something.
>
>      But if I change the True to 1, that's OK.  Also it's hard to debug
> this kind of issue, becuase the trackback not tell me where it happen.
>
>
> Any suggestion?
>
> Regards
> Chriss
>
>
>
> ------------------------------------------------------------------------------
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[myhdl-list] some issue

[<chr...@si...>]

Dear all,
When I using myhdl, I found some issue that could be improvement as following for discussion
A)  information for debug is not enough      For example, I build some basic library.  when something wrong (e.g multiple driven ),  myhdl only report the location happens in the library in conversion, but not tell me where I call the library.
I try to modify the the Error class to add a "node" property, then use "try .. exception" to catch the node information as following.class Error(Exception):
    def __init__(self, kind, msg="", info="",node=None):        self.kind = kind        self.msg = msg        self.info = info        self.node = node   
   The solution is helpful, but not convenient.  It's better to automatically locate the root cause of the error.

B)  In simulation, there is similar issue when use lot of library as issue A.  But I have no ideas to add debug info (need more time to figure out the simulation mechanism, currently not document found)
C) in python 3.5,  the following will report a "n.signed" error ( n has no attribute of "signed")    @myhdl.always_comb     def rtl():         if   a == True:              do_something.
     But if I change the True to 1, that's OK.  Also it's hard to debug this kind of issue, becuase the trackback not tell me where it happen.

Any suggestion?
RegardsChriss

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[myhdl-list] What do I need to do?

[Edward V. <dev...@sb...>]

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Re: [myhdl-list] hi myhdl

[David H. <da...@ad...>]

Yep, DMARC uses SPF and DKIM, and the DMARC records are just as easy to 
set up as SPF.

https://dmarc.org/wiki/FAQ#How_does_DMARC_work.2C_briefly.2C_and_in_non-technical_terms.3F


-- very off-topic from the list now... --

If I recall correctly, you set up SPF (spf1) records to protect the FROM 
(internal SMTP header), and DKIM to protect the displayed From:/Sender:.  
(more or less)

In short sumary, DKIM without SPF, or SPF without DKIM doesn't cover all 
the edge cases of mail sender protection, so DMARC integrates the two 
and adds the ability for the mail server operator to get realtime 
feedback.  Thus, a complete modern mail server uses the combo punch of: 
DMARC+DKIM+SPF+SRS.  (SRS is needed to not break SPF when forwarding 
mail from other sources such as through .forward files.  In this case 
the sender's DKIM signature protects the message contents.)

Here's where I keep a stash of notes-to-self for the various validation 
tests: https://ad5ey.net/domain

And if you're going this far, these DNS records should be protected by 
enabling DNSSEC (use NSEC3) to limit DNS attacks, but once DNSSEC is 
enabled, creating TLSA records is easy and enables opportunistic 
encryption.  I love this effort:
https://datatracker.ietf.org/doc/rfc7672/

(all transparent to end users...)

I'm available to offer any pointers (Bind + Postfix) to interested 
folks, but further discussion should probably be off-list...  ;)

- David


On Thu, Jun 02, 2016 at 04:25:15PM +0100, Mr C Camacho wrote:
>there is spf too which is actually quite easy to set up...
>googled this simple checker http://www.kitterman.com/spf/validate.html
>
>
>On 02/06/16 15:53, David J. Holl, Jr. wrote:
>>Often times, the account in question wasn't hacked, but bots merely 
>>faked the from address along with other mail headers to cover their 
>>tracks. In the original SMTP specs, there's nothing to prevent From 
>>forgery, but in the recent years, DMARC was developed specifically 
>>to allow domain owners to lock down their domains to prevent such 
>>third party forgeries.
>>
>>DMARC has raised some controversy, because for locked-down domains, 
>>it also prevents naive mailing lists from relaying messages --- but 
>>any real list server software today can interoperate with DMARC now.
>>
>>It looks like this domain "djnewmoney.com <http://djnewmoney.com>" 
>>did not publish any DMARC DNS records
>>https://dmarcian.com/record-tools/djnewmoney.com
>>
>>But if it did (and with the underlying SPF and DKIM records, too), 
>>then all other email servers could easily spot and reject these 
>>forgeries.
>>
>>Examples of strict DMARC records:
>>https://dmarcian.com/record-tools/google.com
>>https://dmarcian.com/record-tools/yahoo.com
>>https://dmarcian.com/record-tools/citibank.com
>>https://dmarcian.com/record-tools/paypal.com
>>And my own domains:
>>https://dmarcian.com/record-tools/ad5ey.net
>>
>>Summary: Any domain is at risk for these From forgeries, and I wish 
>>more domain owners would opt into DMARC to stop such schemes.
>>
>>- David
>>
>>On June 2, 2016 7:07:27 AM PDT, Josy Boelen <jos...@gm...> wrote:
>>
>>    develone <develone <at>djnewmoney.com <http://djnewmoney.com>> writes:
>>
>>        Hi myhdl
>>        http://lazarandkalmar.com/division.php?sense=1pn5d4qnxkg2zby1
>>        develone
>>        ------------------------------------------------------------------------
>>
>>    develone,
>>
>>    it looks like you have been hacked!
>>
>>    Regards,
>>
>>    JOsy
>>
>>
>>    ------------------------------------------------------------------------
>>
>>    What NetFlow Analyzer can do for you? Monitors network bandwidth and traffic
>>    patterns at an interface-level. Reveals which users, apps, and protocols are
>>    consuming the most bandwidth. Provides multi-vendor support for NetFlow,
>>    J-Flow, sFlow and other flows. Make informed decisions using capacity
>>    planning reports.https://ad.doubleclick.net/ddm/clk/305295220;132659582;e
>>    ------------------------------------------------------------------------
>>
>>    myhdl-list mailing list
>>    myh...@li...
>>    https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>------------------------------------------------------------------------------
>>What NetFlow Analyzer can do for you? Monitors network bandwidth and traffic
>>patterns at an interface-level. Reveals which users, apps, and protocols are
>>consuming the most bandwidth. Provides multi-vendor support for NetFlow,
>>J-Flow, sFlow and other flows. Make informed decisions using capacity
>>planning reports. https://ad.doubleclick.net/ddm/clk/305295220;132659582;e
>>
>>_______________________________________________
>>myhdl-list mailing list
>>myh...@li...
>>https://lists.sourceforge.net/lists/listinfo/myhdl-list

>------------------------------------------------------------------------------
>What NetFlow Analyzer can do for you? Monitors network bandwidth and traffic
>patterns at an interface-level. Reveals which users, apps, and protocols are
>consuming the most bandwidth. Provides multi-vendor support for NetFlow,
>J-Flow, sFlow and other flows. Make informed decisions using capacity
>planning reports. https://ad.doubleclick.net/ddm/clk/305295220;132659582;e

>_______________________________________________
>myhdl-list mailing list
>myh...@li...
>https://lists.sourceforge.net/lists/listinfo/myhdl-list


-- 
Dr. David Holl, Jr.
President and LLC Member
Subspace Dynamics, LLC
3543 Brook St #101
Lafayette, CA 94549
281-206-4060
dh...@su...

Re: [myhdl-list] hi myhdl

[Mr C C. <ch...@be...>]

there is spf too which is actually quite easy to set up...
googled this simple checker http://www.kitterman.com/spf/validate.html


On 02/06/16 15:53, David J. Holl, Jr. wrote:
> Often times, the account in question wasn't hacked, but bots merely 
> faked the from address along with other mail headers to cover their 
> tracks. In the original SMTP specs, there's nothing to prevent From 
> forgery, but in the recent years, DMARC was developed specifically to 
> allow domain owners to lock down their domains to prevent such third 
> party forgeries.
>
> DMARC has raised some controversy, because for locked-down domains, it 
> also prevents naive mailing lists from relaying messages --- but any 
> real list server software today can interoperate with DMARC now.
>
> It looks like this domain "djnewmoney.com <http://djnewmoney.com>" did 
> not publish any DMARC DNS records
> https://dmarcian.com/record-tools/djnewmoney.com
>
> But if it did (and with the underlying SPF and DKIM records, too), 
> then all other email servers could easily spot and reject these forgeries.
>
> Examples of strict DMARC records:
> https://dmarcian.com/record-tools/google.com
> https://dmarcian.com/record-tools/yahoo.com
> https://dmarcian.com/record-tools/citibank.com
> https://dmarcian.com/record-tools/paypal.com
> And my own domains:
> https://dmarcian.com/record-tools/ad5ey.net
>
> Summary: Any domain is at risk for these From forgeries, and I wish 
> more domain owners would opt into DMARC to stop such schemes.
>
> - David
>
> On June 2, 2016 7:07:27 AM PDT, Josy Boelen <jos...@gm...> wrote:
>
>     develone <develone <at>djnewmoney.com <http://djnewmoney.com>> writes:
>
>         Hi myhdl
>         http://lazarandkalmar.com/division.php?sense=1pn5d4qnxkg2zby1
>         develone
>         ------------------------------------------------------------------------
>
>     develone,
>
>     it looks like you have been hacked!
>
>     Regards,
>
>     JOsy
>
>
>     ------------------------------------------------------------------------
>
>     What NetFlow Analyzer can do for you? Monitors network bandwidth and traffic
>     patterns at an interface-level. Reveals which users, apps, and protocols are
>     consuming the most bandwidth. Provides multi-vendor support for NetFlow,
>     J-Flow, sFlow and other flows. Make informed decisions using capacity
>     planning reports.https://ad.doubleclick.net/ddm/clk/305295220;132659582;e
>     ------------------------------------------------------------------------
>
>     myhdl-list mailing list
>     myh...@li...
>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
> ------------------------------------------------------------------------------
> What NetFlow Analyzer can do for you? Monitors network bandwidth and traffic
> patterns at an interface-level. Reveals which users, apps, and protocols are
> consuming the most bandwidth. Provides multi-vendor support for NetFlow,
> J-Flow, sFlow and other flows. Make informed decisions using capacity
> planning reports. https://ad.doubleclick.net/ddm/clk/305295220;132659582;e
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] hi myhdl

[Josy B. <jos...@gm...>]

develone <develone <at> djnewmoney.com> writes:

> 
> Hi myhdl
> 
> http://lazarandkalmar.com/division.php?sense=1pn5d4qnxkg2zby1
> 
> develone
> 
> ------------------------------------------------------------------------
develone,

it looks like you have been hacked!

Regards,

JOsy

[myhdl-list] hi myhdl

[develone <dev...@dj...>]

Hi myhdl

http://lazarandkalmar.com/division.php?sense=1pn5d4qnxkg2zby1



develone

Re: [myhdl-list] Support for port mapping during conversion to Verilog and some general doubts

[Samuele D. <sm...@gm...>]

Hi,
This is the development version http://docs.myhdl.org/en/latest/.
You should start from here because 1.0 is not so far from being tagged and
it will break compatibility with old code. See
http://docs.myhdl.org/en/latest/whatsnew/1.0.html.

On Sun, May 29, 2016 at 9:29 AM, Vineesh V S <vin...@ho...> wrote:

> Dear myHDL Admin/ users,
>
>
>
>    1. Is 'port mapping' facility available in myHDL? When I tried
>    creating instances of blocks it was making multiple copies of the full
>    block with different names for variables.
>    2. Where can I get the latest manual for myHDL? Is the one given in
>    http://old.myhdl.org/doku.php/doc:pdf the latest one?
>
>
> Thanks
>
>
> ------------------------------------------------------------------------------
> What NetFlow Analyzer can do for you? Monitors network bandwidth and
> traffic
> patterns at an interface-level. Reveals which users, apps, and protocols
> are
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[myhdl-list] Support for port mapping during conversion to Verilog and some general doubts

[Vineesh V S <vin...@ho...>]

      
          Dear myHDL Admin/ users,




Is 'port mapping' facility available in myHDL? When I tried creating
 instances of blocks it was making multiple copies of the full block 
with different names for variables.Where can I get the latest manual for myHDL? Is the one given in http://old.myhdl.org/doku.php/doc:pdf the latest one?


Thanks

      
     		 	   		  

Re: [myhdl-list] Block return values (myhdl.BlockError)

[Jan D. <ja...@ja...>]

On 13/05/16 16:45, Jos Huisken wrote:
> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>
>> I have nothing against collecting good ideas.
>>
>> However, for this specific feature, I am unconvinced
>> that the additional complexity is warranted. I may
>> change that opinion with future evidence - until
>> now it has only been brought up once as an alternative
>> possibility and does not seem enough.
>
> I didn't expect to raise such discussion ;-), and I guess we have to give
> it more thought. I have used all kinds of return values, next to Signals,
> especially in testbenches. The example I showed was a small part of a
> template based testbench+design which I will revisit, hopefully soon,
> with the current simplification.

For the record: the problem is limited to the return
values of blocks themselves. You will need to use
blocks for certain applications, but you are not
forced to use them for all modeling applications.

You can still use blocks within non-blocks and then
do whatever you want in terms of return values or
other sophisticated techniques.

The current Simulation API will remain available
to simulate such cases, in test benches or for
high-level modeling.

Blocks are merely intended to make hiearchy extraction
easier and much more robust, as needed for the important
sub-applications of conversion and signal tracing.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
   Python as a HDL: http://www.myhdl.org
   VHDL development, the modern way: http://www.sigasi.com
   Urubu, a static website CMS: http://urubu.jandecaluwe.com

Re: [myhdl-list] Block return values (myhdl.BlockError)

[Henry G. <he...@ma...>]

On 13/05/16 15:45, Jos Huisken wrote:
> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
> 
>> > I have nothing against collecting good ideas.
>> > 
>> > However, for this specific feature, I am unconvinced
>> > that the additional complexity is warranted. I may
>> > change that opinion with future evidence - until
>> > now it has only been brought up once as an alternative
>> > possibility and does not seem enough.
> I didn't expect to raise such discussion ;-), and I guess we have to give 
> it more thought. I have used all kinds of return values, next to Signals, 
> especially in testbenches. The example I showed was a small part of a 
> template based testbench+design which I will revisit, hopefully soon,  
> with the current simplification.
> 

Do you have any of this code to share?

I've made an attempt with Veriutils
(https://github.com/hgomersall/Veriutils) to solve the problem of HDL
tests needing lots of boilerplate (think random vectors, clock
generators, reset initialisation) and integrating that with a framework
for a poor man's cosimulation (when the tools don't allow "proper"
cosimulation e.g. Vivado), by recording MyHDL signals and playing them
back inside the testbench.

I'm interested to know about alternative tools to make the process of
verification simpler and more robust.

Cheers,

Henry

Re: [myhdl-list] Block return values (myhdl.BlockError)

[Jos H. <jos...@gm...>]

Jan Decaluwe <jan <at> jandecaluwe.com> writes:

> I have nothing against collecting good ideas.
> 
> However, for this specific feature, I am unconvinced
> that the additional complexity is warranted. I may
> change that opinion with future evidence - until
> now it has only been brought up once as an alternative
> possibility and does not seem enough.

I didn't expect to raise such discussion ;-), and I guess we have to give 
it more thought. I have used all kinds of return values, next to Signals, 
especially in testbenches. The example I showed was a small part of a 
template based testbench+design which I will revisit, hopefully soon,  
with the current simplification.

> My priority is moving forward with the simplifications
> enabled by  <at> block, and I believe there are several
> much more relevant new features that these simplifications
> will make possible.
> 
> Jan
> 

[myhdl-list] Tristate 8 bit bi-directional

[Edward V. <dev...@sb...>]

Hello All
I came across Josy Boelen simpletristateexample.py.

Josy code works great. 

I started from his code and created mul_ts.py
https://gist.github.com/441d86f67d3fdac12d53d1f93e44fcea.git
in hopes of getting to a 8 bit Bi-directional Signal.

I import his simpletristateexample.py
https://gist.github.com/c816d585e12ae397627b.git

My code converts and I can simulate with the
following cmds python mul_ts.py --convert &
python mul_ts.py --trace

When I uncoment lines 73-75 my code.
        '''
        @always_comb
        def rtl2():
            t_rpi2B.next = concat(ts7,ts6,ts5,ts4,ts3,ts2,ts1,ts0)
        ''' 

My code will not convert or trace.
This is the error that I get.
    t_rpi2B.next = concat(ts7,ts6,ts5,ts4,ts3,ts2,ts1,ts0)
  File "/usr/local/lib/python2.7/dist-packages/myhdl-1.0dev-py2.7.egg/myhdl/_concat.py", line 79, in concat
    val = val << w | v & (long(1) << w)-1
TypeError: unsupported operand type(s) for <<: 'NoneType' and 'int'

I have also tried which converts but will not trace
        @always_comb
        def rtl2():
            t_rpi2B.next = ts7*128+ts6*64+ts5*32+ts4*16+ts3*8+ts2*4+ts1*2+ts0
With this error
    t_rpi2B.next = ts7*128+ts6*64+ts5*32+ts4*16+ts3*8+ts2*4+ts1*2+ts0
  File "/usr/local/lib/python2.7/dist-packages/myhdl-1.0dev-py2.7.egg/myhdl/_Signal.py", line 379, in __mul__
    return self._val * other
TypeError: unsupported operand type(s) for *: 'NoneType' and 'int'
 
My issue is that I can not combine the 8 tristate signals
to a bus.
I appreciate any help. Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] Block return values (myhdl.BlockError)

[Henry G. <he...@ma...>]

On 10/05/16 13:09, Henry Gomersall wrote:
> On 10/05/16 12:30, Jan Decaluwe wrote:
>> > On 10/05/16 12:02, Henry Gomersall wrote:
>>>> >> > On 10/05/16 10:45, Henry Gomersall wrote:
>>>>>> >>> >> On 10/05/16 10:32, Jan Decaluwe wrote:
>>>>>>>>>> >>>>> >>>> I have considered this issue for some time now
>>>>>>>>>> >>>>> >>>> and I have basically decided to leave the constraints
>>>>>>>>>> >>>>> >>>> as they are, that is, blocks should only return
>>>>>>>>>> >>>>> >>>> block and instantiator objects.
>>>>>> >>> >> I think your reasoning is sound.
>>>>>> >>> >>
>>>>>> >>> >> Do you object to alternative strategies for constructing Block
>>>>>> >>> >> operators? This could leave @block as the default usual case, with more
>>>>>> >>> >> esoteric cases handled by direct access to the construction of the Block
>>>>>> >>> >> object. This could allow the best of both worlds - simple default and
>>>>>> >>> >> arbitrary control if desired.
>>>> >> >
>>>> >> > Actually, a neat solution could be to allow optional decorator arguments
>>>> >> > taking the class constructor and allow subclassing of _Block.
>>>> >> >
>> > Independent of this feature, decorator arguments may be
>> > useful, but as you know a decorator without arguments
>> > behaves completely differently from a decorator with
>> > arguments.
>> > 
>> > Until now, the only way I saw to handle both cases
>> > with a single decorator was with some ad-hoc check
>> > that I didn't find very elegant.
> Yeah this is an issue. There's a somewhat neat way using keyword args
> exclusively, but it does require keyword args (which is not overly
> restrictive since this would be an "advanced" feature).
> 
> In this case it might work reasonably neatly in the simpler case though
> since we can check it's either a callable or a _Block, and reject
> anything else.

To be clear, what is seen by a naive user need not changed.

Both @block and @block(MyCustomBlock) can be made to work.

Speaking of that, another solution is to have something like an
@custom_block() decorator which _must_ take an argument.

Henry

Re: [myhdl-list] Block return values (myhdl.BlockError)

[Henry G. <he...@ma...>]

On 10/05/16 12:30, Jan Decaluwe wrote:
> On 10/05/16 12:02, Henry Gomersall wrote:
>> > On 10/05/16 10:45, Henry Gomersall wrote:
>>> >> On 10/05/16 10:32, Jan Decaluwe wrote:
>>>>> >>>> I have considered this issue for some time now
>>>>> >>>> and I have basically decided to leave the constraints
>>>>> >>>> as they are, that is, blocks should only return
>>>>> >>>> block and instantiator objects.
>>> >> I think your reasoning is sound.
>>> >>
>>> >> Do you object to alternative strategies for constructing Block
>>> >> operators? This could leave @block as the default usual case, with more
>>> >> esoteric cases handled by direct access to the construction of the Block
>>> >> object. This could allow the best of both worlds - simple default and
>>> >> arbitrary control if desired.
>> >
>> > Actually, a neat solution could be to allow optional decorator arguments
>> > taking the class constructor and allow subclassing of _Block.
>> >
> Independent of this feature, decorator arguments may be
> useful, but as you know a decorator without arguments
> behaves completely differently from a decorator with
> arguments.
> 
> Until now, the only way I saw to handle both cases
> with a single decorator was with some ad-hoc check
> that I didn't find very elegant.

Yeah this is an issue. There's a somewhat neat way using keyword args
exclusively, but it does require keyword args (which is not overly
restrictive since this would be an "advanced" feature).

In this case it might work reasonably neatly in the simpler case though
since we can check it's either a callable or a _Block, and reject
anything else.

Henry

Re: [myhdl-list] Block return values (myhdl.BlockError)

[Jan D. <ja...@ja...>]

On 10/05/16 12:02, Henry Gomersall wrote:
> On 10/05/16 10:45, Henry Gomersall wrote:
>> On 10/05/16 10:32, Jan Decaluwe wrote:
>>>> I have considered this issue for some time now
>>>> and I have basically decided to leave the constraints
>>>> as they are, that is, blocks should only return
>>>> block and instantiator objects.
>> I think your reasoning is sound.
>>
>> Do you object to alternative strategies for constructing Block
>> operators? This could leave @block as the default usual case, with more
>> esoteric cases handled by direct access to the construction of the Block
>> object. This could allow the best of both worlds - simple default and
>> arbitrary control if desired.
>
> Actually, a neat solution could be to allow optional decorator arguments
> taking the class constructor and allow subclassing of _Block.
>

Independent of this feature, decorator arguments may be
useful, but as you know a decorator without arguments
behaves completely differently from a decorator with
arguments.

Until now, the only way I saw to handle both cases
with a single decorator was with some ad-hoc check
that I didn't find very elegant.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
   Python as a HDL: http://www.myhdl.org
   VHDL development, the modern way: http://www.sigasi.com
   Urubu, a static website CMS: http://urubu.jandecaluwe.com

Re: [myhdl-list] Block return values (myhdl.BlockError)

[Jan D. <ja...@ja...>]

On 10/05/16 11:45, Henry Gomersall wrote:
> On 10/05/16 10:32, Jan Decaluwe wrote:
>> I have considered this issue for some time now
>> and I have basically decided to leave the constraints
>> as they are, that is, blocks should only return
>> block and instantiator objects.
>
> I think your reasoning is sound.
>
> Do you object to alternative strategies for constructing Block
> operators? This could leave @block as the default usual case, with more
> esoteric cases handled by direct access to the construction of the Block
> object. This could allow the best of both worlds - simple default and
> arbitrary control if desired.

I have nothing against collecting good ideas.

However, for this specific feature, I am unconvinced
that the additional complexity is warranted. I may
change that opinion with future evidence - until
now it has only been brought up once as an alternative
possibility and does not seem enough.

My priority is moving forward with the simplifications
enabled by @block, and I believe there are several
much more relevant new features that these simplifications
will make possible.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
   Python as a HDL: http://www.myhdl.org
   VHDL development, the modern way: http://www.sigasi.com
   Urubu, a static website CMS: http://urubu.jandecaluwe.com